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MC14011B/12B (see pg 6-5)
SEMICONDUCTOR TECHNICAL DATA
MC14011UB/12UB (see pg 6-14)
MC14013B
Dual Type D Flip-Flop
The MC14013B dual type D flip–flop is constructed with MOS P–channel
and N–channel enhancement mode devices in a single monolithic structure.
Each flip–flop has independent Data, (D), Direct Set, (S), Direct Reset, (R), and Clock (C) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip–flops for counter and toggle applications.
Static Operation
Diode Protection on All Inputs
Supply Voltage Range = Vdc to 18 Vdc
Logic Edge–Clocked Flip–Flop Design
Logic state is retained indefinitely with clock level either high or low;
information is transferred to the output only on the positive–going edge
of the clock pulse
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Ratedemperature T Range
Pin–for–Pin Replacement for CD4013B
MAXIMUM RATINGS*
SS
(Voltages Referenced to V )
Symbol
Parameter
Value
Unit
VDD
DC Supply Voltage
– to +
V
V
, V
Input or Output Voltage (DC or Transient) – to V +
V
in out
DD
l
, l
Input or Output Current (DC or Transient),
± 10
mA
in
out
per Pin
PD
Power Dissipation, per Package†
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature (8–Second Soldering)
260
_C
Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating: Plastic “P and D/DW” Packages: – mW/C From 65C To 125_C Ceramic “L” Packages: – 12 mW/C From 100C To 125_C
TRUTH TABLE
Inputs
Outputs
Clock†
Data
Reset
Set
Q
Q
0
0
0
0
1
1
0
0
1
0
No
X
0
0
Q
Q
Change
X
X
1
0
0
1
X
X
0
1
1
0
X
X
1
1
1
1
X = Don’t Care
† = Level Change
REV 3
1/94
©MOTOROLA Motorola, Inc . CMOS1995 LOGIC DATA
L SUFFIX
CERAMIC
CASE 632
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
TA = – 55° to 125°C for all packages.
BLOCK DIAGRAM
6
5
D
S
1
Q
3
C
Q
2
R
4
8
9
D
S
13
Q
11
C
Q
12
R
10
VDD = PIN 14
VSS = PIN 7
MC14013B
45
ELECTRICAL CHARACTERISTICS
SS
)
(Voltages Referenced to V
VDD
– 55_C
25_C
125_C
Characteristic
Symbol
Vdc
Min
Max
Min
Typ #
Max
Min
Max
Unit
Output Voltage
“0” Level
VOL
—
—
0
—
Vdc
V
= V or 0
10
—
—
0
—
in
DD
15
—
—
0
—
V
= 0 or V
“1” Level
V
OH
—
—
—
Vdc
in
DD
10
—
10
—
—
15
—
15
—
—
Input Voltage “0” Level (VO = or Vdc) (VO = or Vdc) (VO = or Vdc)
(VO = or Vdc)“1” Level (VO = or Vdc) (VO = or Vdc)
Output Drive Current
(VOH = Vdc) Source (VOH = Vdc) (VOH = Vdc) (VOH = Vdc)
(VOL = Vdc) Sink (VOL = Vdc) (VOL = Vdc)
Input Current
Input Capacitance
(Vin = 0)
VIL
—
—
—
Vdc
10
—
—
—
15
—
—
—
VIH
—
—
—
Vdc
10
—
—
—
15
11
—
11
—
11
—
IOH
–
—
–
–
—
–
—
mAdc
–
—
–
–
—
–
—
10
–
—
–
–
—
–
—
15
–
—
–
–
—
–
—
IOL
—
—
—
mAdc
10
—
—
—
15
—
—
—
Iin
15
—
±
—
±
±
—
±
µAdc
Cin
—
—
—
—
—
—
pF
Quiescent Current
IDD
—
—
—
30
µAdc
(Per Package)
10
—
—
—
60
15
—
—
—
120
Total Supply Current**†
I
I = (µA/kHz) f + I
µAdc
(Dynamic plus Quiescent,
T
10
T
DD
I = (µA/kHz) f + I
Per Package)
15
T
DD
I = (µA/kHz) f + I
(CL = 50 pF on all outputs, all
T
DD
buffers switching)
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
**The formulas given are for the typical characteristics only atC 25.
†To calculate total supply current at loads other than 50 pF:
I
(C
) = I (50 pF) + (C – 50) Vfk
T
L
T
L
where: I is inµA (per package), C in pF, V = (V
– V
) in volts, f in kHz is input frequency, and k = .
T
L
DD
SS
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, nV and Vout should be constrained to the rangeSS V ≤ (Vin or Vout) ≤ VDD.
Unused inputs must always be tied to an appropriate logic voltage level (., either VSS or VDD). Unused outputs must be left open.
PIN ASSIGNMENT
QA
1
14
VDD
QA
2
13
QB
CA
3
12
QB
RA
4
11
CB
DA
5
10
RB
SA
6
9
DB
VSS
7
8
SB
MC14013B
MOTOROLA CMOS LOGIC DATA
46
SWITCHING CHARACTERISTICS*
L
A
(C = 50 pF, T = 25C)
Characteristic
Symbol
Output Rise and Fall Time
tTLH,
t
, t
= ( ns/pF) C + 25 ns
t
TLH
THL
L
THL
t
, t
= ( ns/pF) C + ns
TLH
THL
L
t
, t
= ( ns/pF) C + ns
TLH
THL
L
Propagation Delay Time
tPLH
Clock to Q, Q
tPHL
t
, t
= ( ns/pF) C + 90 ns
PLH
PHL
L
t
, t
= ( ns/pF) C + 42 ns
PLH
PHL
L
t
, t
= ( ns/pF) C + 25 ns
PLH
PHL
L
Set to Q, Q
t
, t
= ( ns/pF) C + 90 ns
PLH
PHL
L
t
, t
= ( ns/pF) C + 42 ns
PLH
PHL
L
t
, t
= ( ns/pF) C + 25 ns
PLH
PHL
L
Reset to Q, Q
t
, t
= ( ns/pF) C + 265 ns
PLH
PHL
L
t
, t
= ( ns/pF) C + 67 ns
PLH
PHL
L
t
, t
= ( ns/pF) C + 50 ns
PLH
PHL
L
Setup Times**
tsu
Hold Times**
th
Clock Pulse Width
tWL, tWH
Clock Pulse Frequency
fcl
Clock Pulse Rise and Fall Time
tTLH
tTHL
Set and Reset Pulse Width
tWL, tWH
Removal Times
trem
Set
Reset
VDD
Min
Typ #
Max
Unit
—
ns
100
200
10
—
50
100
15
—
40
80
ns
—
175
350
10
—
75
150
15
—
50
100
—
175
350
10
—
75
150
15
—
50
100
—
225
450
10
—
100
200
15
—
75
150
40
20
—
ns
10
20
10
—
15
15
—
40
20
—
ns
10
20
10
—
15
15
—
250
125
—
ns
10
100
50
—
15
70
35
—
—
MHz
10
—
10
15
—
14
—
—
15
µs
10
—
—
15
—
—
250
125
—
ns
10
100
50
—
15
70
35
—
ns
5
80
0
—
10
45
5
—
15
35
5
—
5
50
– 35
—
10
30
– 10
—
15
25
– 5
—
The formulas given are for the typical characteristics only atC 25. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. **Data must be valid for 250 ns with a 5 V supply, 100 ns with, and 10 70V ns with 15. V
LOGIC DIAGRAM
(1/2 of Device Shown)
S
C C Q
D
C C Q
C C
C C
C C
C
R
MOTOROLA CMOS LOGIC DATA
MC14013B
47
20 ns
20 ns
VDD
D
90%
50%
20 ns
20 ns
t (H)
10%
t
VSS
VDD
su(L)
SET OR 90%
su
th
90%
20 ns
50%
C
VDD
RESET
10%
VSS
50%
tw
trem
10%
VSS
20 ns
tWH
20 ns
VDD
tWL
90%
1
CLOCK
50%
10%
VSS
tPLH
fcl
tPHL
tPLH
tw
VOH
Q
90%
tPHL
VOH
50%
10%
VOL
Q OR Q
50%
VOL
tTLH
tTHL
Inputs R and S low.
Figure 1. Dynamic Signal Waveforms
Figure 2. Dynamic Signal Waveforms
(Data, Clock, and Output)
(Set, Reset, Clock, and Output)
TYPICAL APPLICATIONS
n–STAGE SHIFT REGISTER
1 2 nth
D D Q D Q D Q Q
C Q C Q C Q
CLOCK
BINARY RIPPLE UP–COUNTER (Divide–by–2n)
1 2 nth
D Q D Q D Q Q
CLOCK C Q C Q C Q
T FLIP–FLOP
MODIFIED RING COUNTER(Divide–by–(n+1))
1 2 nth
D Q D Q D Q Q
C Q C Q C Q
CLOCK
MC14013B MOTOROLA CMOS LOGIC DATA
48
OUTLINE DIMENSIONS
L SUFFIX
CERAMIC DIP PACKAGE
CASE 632–08
–A–
ISSUE Y
14
9
–B–
1
7
C
L
–T–
K
SEATING
PLANE
F
G
N
M
D 14 PL
J
14 PL
()M T A S
()M T B S
P SUFFIX
PLASTIC DIP PACKAGE
CASE 646–06
ISSUE L
14
8
B
1
7
A
F
L
C
N
J
SEATINGK
H
G
D PLANE
M
NOTES:
AND TOLERANCING PER ANSI
, 1982.
DIMENSION: INCH.
L TO CENTER OF LEAD WHEN FORMED PARALLEL.
F MAY NARROW TO ()
WHERE THE LEAD ENTERS THE CERAMIC
BODY.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A
B
C
D
F
G
BSC BSC
J
K
L
BSC BSC
M
0_ 15 0_ 15
N
NOTES:
WITHIN () RADIUS OF TRUE
POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION.
L TO CENTER OF LEADS WHEN FORMED PARALLEL.
B DOES NOT INCLUDE MOLD FLASH.
CORNERS OPTIONAL.
INCHES
MILLIMETERS
DIM MIN MAX MIN MAX
A
B
C
D
F
G
BSC BSC
H
J
K
L
BSC BSC
M
0_
10
0_
10
N
MOTOROLA CMOS LOGIC DATA
MC14013B
49
OUTLINE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A–03
ISSUE F
NOTES:
–A–
AND TOLERANCING PER ANSI
, 1982.
DIMENSION: MILLIMETER.
A AND B DO NOT INCLUDE
14
8
MOLD PROTRUSION.
MOLD PROTRUSION ()
–B–