文档介绍：基于FPGA的DDS应用设计
摘要
本文以FPGA 为平台,介绍了DDS 的基本原理,DDS 的FPGA 实现方案。在传统DDS 的基础上提出改进措施,使得DDS 具有更高的输出分辨率和波形存储器利用率。在信号发生器的设计中,传统的用分立元件或通用数字电路元件设计电子线路的方法设计周期长,花费大,可移植性差。本设计是利用EDA技术设计的电路, 该信号发生器输出信号的频率范围为20Hz~20KHz,幅度的峰-~5V两路信号之间可实现0°~359°的相位差。
本文侧重叙述了用FPGA来完成直接数字频率合成器(DDS)的设计,DDS由相位累加器和正弦ROM查找表两个功能块组成,其中ROM查找表由兆功能模块LPM_ROM来实现。而通过设定不同的累加器初值(K1)和初始相位值(K2),可以调节两路相同频率正弦信号之间的相位差,从而产生两路数字式的频率、相位和幅值可调的正弦波信号,最后通过QUARTUS II下载。
关键词: FPGA DDS 信号发生器 ROM
Abstract
This paper describes the basic principle of DDS, proposes the solution of DDS byFPGA. Improvements are given based on the tranditional DDS which allow DDS having higheroutput resolution and higher efficiency of memory utilization ratio.
In the designing of the signal generator, the traditional method, which designs electronic circuits using ponents or general digital ponents, takes a long time with high cost, what’s more, the transplanting ability of it is unsatisfactory. In this design, the circuit is designed by means of EDA. Its output frequency range is 20Hz to 20KHz with an output amplitude range of to 5V(P-P), and the phase difference between two outputs of the two sine signals can be modulated from 0°to 359°.
The thesis emphasizing discusses the designing of DDS basing on FPGA. DDS is made up of the phrase accumulator and sine ROM looking-up table, which is realized by functional EAB chip. And through setting different initial accumulator value (K1) and initial phrase value (K2), the difference of phrase between the two sine signals can be changed. As a result, two serials of sine signals with changeable digital frequency, phrase and magnitude are produced. At last, we can show the total course and result with QUARTUS II.
Keywords: FPGA DDS Signal Generator ROM
目录
绪论 1
第一章 DSS的原理及应用方案 3
3
DDS的基本原理及性能特点 3
DDS 的实现方案 6
第二章硬件开发的原理 9
FPGA概述 9
FPGA的基本特点 9
FPGA配置方式 9
FPGA和CPLD的区别 11
VHDL 语言 12
QUARTUS II简介 13
第三章其他设计电路及器件介绍 15
15
D/