文档介绍：Introduction to CMOS VLSI Design Lecture 15: Nonideal Transistors
David Harris
Harvey Mudd College
Spring 2004
1
15: Nonideal Transistors
Outline
Transistor I-V Review
Nonideal Transistor Behavior
Velocity Saturation
Channel Length Modulation
Body Effect
Leakage
Temperature Sensitivity
Process and Environmental Variations
Process Corners
2
15: Nonideal Transistors
Ideal Transistor I-V
Shockley 1st order transistor models
3
15: Nonideal Transistors
Ideal nMOS I-V Plot
180 nm TSMC process
Ideal Models
b = 155(W/L) mA/V2
Vt = V
VDD = V
4
15: Nonideal Transistors
Simulated nMOS I-V Plot
180 nm TSMC process
BSIM 3v3 SPICE models
What differs?
5
15: Nonideal Transistors
Simulated nMOS I-V Plot
180 nm TSMC process
BSIM 3v3 SPICE models
What differs?
Less ON current
No square law
Current increases
in saturation
6
15: Nonideal Transistors
Velocity Saturation
We assumed carrier velocity is proportional to E-field
v = mElat = mVds/L
At high fields, this ceases to be true
Carriers scatter off atoms
Velocity reaches vsat
Electrons: 6-10 x 106 cm/s
Holes: 4-8 x 106 cm/s
Better model
7
15: Nonideal Transistors
Vel Sat I-V Effects
Ideal transistor ON current increases with VDD2
Velocity-saturated ON current increases with VDD
Real transistors are partially velocity saturated
Approximate with a-power law model
Ids VDDa
1 < a < 2 determined empirically
8
15: Nonideal Transistors
a-Power Model
9
15: Nonideal Transistors
Channel Length Modulation
Reverse-biased p-n junctions form a depletion region
Region between n and p with no carriers
Width of depletion Ld region grows with reverse bias
Leff = L – Ld
Shorter Leff gives more current
Ids increases with Vds
Even in saturation
10
15: Nonideal Transistors