文档介绍：International Journal of Electronics
Vol. 95, No. 9, September 2008, 891902
Proposal of Synthesizable analogue-to-digital converters from VHDL-AMS
G. Doménech-Asensi* and J. Garrigós-Guerrero
Departamento de Electrónica, ologı´a putadoras y Proyectos, Universidad ica de
Cartagena, Cartagena, 30202, Spain
(Received 9 June 2006; final version received 30 June 2008)
In this article, a procedure to describe synthesisable n-bits analogue-to-digital converters (ADC)
using VHDL-AMS is presented. The aim is to propose specifications for reusable code generation
which makes designers’ tasks easier, shows clearly the underlying hardware structures, and is easily
synthesisable by CAD-EDA tools. Two different architectures of ADC have been developed in
order to show the guidelines for VHDL-AMS descriptions: a flash ADC and a serial ADC. Both
descriptions meet the aforementioned conditions. In order to validate the synthesis methodology we
have adapted a CAD-EDA tool specifically devoted to reconfigurable technology synthesis. We
have synthesised a flash converter on bination of FPGA and FPAA and the results have been
measured in real devices.
Keywords: VHDL; VHDL-AMS; electronic design automation; analogue digital converter; FPGA;
FPAA
1. Introduction
Nowadays the microelectronics market is characterised by an plexity and integrat