文档介绍：一种10位,5MHz流水线型ADC的设计与分析
程梦璋,景为平+
(南通大学,江苏省专用集成电路重点实验室江苏南通 226007)
【摘要】设计和分析了一种具有10位分辨率,5MHz采样频率流水线式模数转换器。。除了最后一级之外,每一级子模数转换器都具有基本相同的电路,可以大大的简化模数转换器的设计和节省时间。电路设计主要包括一种开关采样差分折叠式共源共栅增益级、包括两个时钟控制动态比较器组成的两位模数转换器、两位数模转换器。由于采用了电容下极板采样、全差分和开关栅电压自举,有效的消除了开关管的电荷注入效应、时钟馈通效应引起的采样信号的误差、提高了模数转换器的线性度、信噪比、转换精度和速度。µm CMOS工艺下实现,转换器在采样频率为5 MHz时功耗为70mW,采样500KHz正弦波信号的SFDR为80dB。
关键词流水线; 采样/保持电路; 折叠式; 信噪比
中图分类号 TN402 文献标识码 A
The Design and Analysis of A 10-bit, 5MS/s Pipelined ADC
Cheng Mengzhang,Jing Weiping+
(Nantong University, Jiangsu Province Key Lab of ASIC Design,Jiangsu, Nantong, 226007)
Abstract A 10-bit, 5MHz pipelined ADC was designed. It posed of eight stages with -bit per stage and a 2-bit stage as last stage. Except of last stage, all stages are almost same, therefore which can be used to simple the design of ADC and save designing period. The key circuit design includes: a switch sample/hold differential mon source, common gate op amp,a two-bit ADC and a two-bit DAC. The capacitance bottom plate sampling technique, the fully differential structure and the bootstrapped switch technique are employed, which could cancel the charge injection error of switch MOSFET; decrease the area of chip and eliminate the effect of clock feed-through, improve the linearity, SNR, resolution and speed of the ADC. The ADC have been simulated in µm C