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vhdl语言编程实例.doc

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vhdl语言编程实例.doc

上传人:mh900965 2018/3/20 文件大小:53 KB

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文档介绍:实现各种逻辑功能:
LIBRARY IEEE;
USE ;
USE ;
ENTITY louji1a IS
PORT(S: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
C: IN STD_LOGIC;
A: IN STD_LOGIC_VECTOR(4 DOWNTO 0);
B: IN STD_LOGIC_VECTOR(4 DOWNTO 0);
F: OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
);
END ENTITY louji1a;
ARCHITECTURE ONE OF louji1a IS
BEGIN
F<=A WHEN S="000" ELSE
A-B WHEN S="001" ELSE
A-1 WHEN (S="010" AND C='0') ELSE
A+1 WHEN (S="011" AND C='0') ELSE
A AND B WHEN S="100" ELSE
A OR B WHEN S="101" ELSE
A XOR B WHEN S="110" ELSE
NOT A WHEN S="111" ELSE
NULL;
END ARCHITECTURE ONE;
38译码器:
LIBRARY IEEE;
USE ;
ENTITY yimaqi1a IS
PORT(A: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
B: OUT STD_LOGIC_VECTOR(6 DOWNTO 0)
);
END ENTITY yimaqi1a;
ARCHITECTURE one OF yimaqi1a IS
--SIGNAL abc:STD_LOGIC_VECTOR(3 DOWNTO 0);
--SIGNAL def:STD_LOGIC_VECTOR(6 DOWNTO 0);
BEGIN
--abc<=A3&A2&A1&A0;
--def<=g&f&e&d&c&b&a;
PROCESS (A)
BEGIN
case A IS
WHEN"0000"=>B<="0111111";
WHEN"0001"=>B<="0000110";
WHEN"0010"=>B<="1011011";
WHEN"0011"=>B<="1001111";
WHEN"0100"=>B<="1100110";
WHEN"0101"=>B<="1101101";
WHEN"0110"=>B<="1111101";
WHEN"0111"=>B<="0000111";
WHEN"1000"=>B<="1111111";
WHEN"1001"=>B<="1101111";
WHEN"1010"=>B<="1110111";
WHEN"1011"=>B<="1111100";
WHEN"1100"=>B<="0111001";
WHEN"1101"=>B<="1011110";
WHEN"1110"=>B<="1111001";
WHEN"1111"=>B<="1110001";
WHEN OTHERS =>NULL;
END CASE ;
END PROCESS;
END ARCHITECTURE ONE;
十进制计数器:
LIBRARY IEEE;
USE ;
USE ;
ENTITY jishuqi1a IS
PORT(CLK,EN,CTRL,CLR:IN STD_LOGIC;
Q:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CO:OUT STD_LOGIC);
END ENTITY jishuqi1a;
ARCHITECTURE BHV OF jishuqi1a IS
SIGNAL QQ :STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK,EN,CTRL,CLR)
--VARIABLE QQ :STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
IF CLR='0' THEN QQ<="0000";
ELSIF CTRL='0' THEN QQ<="0000";
ELSIF CLK'EVENT AND CLK='1'
THEN IF EN='1' THEN I