文档介绍：ASICs...THE COURSE (1 WEEK)
ASIC 15
CONSTRUCTION
Key terms and concepts:
• A microelectronic system (or system on a chip) is the town and ASICs (or system
blocks) are the buildings
• System partitioning corresponds to town planning.
• Floorplanning is the architect’s job.
• Placement is done by the builder.
• Routing is done by the electrician.
Physical Design
Key terms and concepts: Divide and conquer • system partitioning • floorplanning • chip planning
• placement • routing • global routing • detailed routing
CAD Tools
Key terms and concepts: goals and objectives for each physical design step
System partitioning:
• Goal. Partition a system into a number of ASICs.
• Objectives. Minimize the number of external connections between the ASICs. Keep each
ASIC smaller than a maximum size.
Floorplanning:
• Goal. Calculate the sizes of all the blocks and assign them locations.
• Objective. Keep the highly connected blocks physically close to each other.
Placement:
• Goal. Assign the interconnect areas and the location of all the logic cells within the
flexible blocks.
• Objectives. Minimize the ASIC area and the interconnect density.
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2 SECTION 15 ASIC CONSTRUCTION ASICS... THE COURSE
Design entry
Part of an ASIC design flow showing the
VHDL/Verilog
system partitioning, floorplanning, place-
ment, and routing steps. Synthesis
These steps may be performed in a slight- netlist
ly different order, iterated or omitted de-
pending on the type and size of the system
System
and its ASICs. partitioning
As the focus shifts from logic to intercon-
nect, floorplanning assumes an increasing-
ly important role. Floorplanning
Each of the steps shown in the figure must chip
be performed and each depends on the
previous step.
Placement
However, the trend is pleting block
these steps in a parallel fashion and iterat-
ing, rather than in a sequential manner.
Routing
logic cells
Global routing:
• Goa