文档介绍：Page 42 Tuesday, April 16, 2002 9:12 AM
CHAPTER
10
TIMING ISSUES
IN DIGITAL CIRCUITS
Impact of clock skew and jitter on performance and functionality
n
Alternative timing methodologies
n
Synchronization issues in digital IC and board design
n
Clock generation
Introduction Synchronizers and Arbiters*
Classification of Digital Systems Clock Synthesis and Synchronization Using a
Phase-Locked Loop
Synchronous Design — An In-depth
Perspective Future Directions
Timing Basics Perspective: Synchronous versus
Asynchronous Design
of Skew and Jitter
Summary
-Distribution Techniques
Probe Further
-Based Clocking
Self-Timed Circuit Design*
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43 TIMING ISSUES IN DIGITAL CIRCUITS Chapter 10
Introduction
All sequential circuits have one property mon—a well-defined ordering of the
switching events must be imposed if the circuit is to operate correctly. If this were not the
case, wrong data might be written into the memory elements, resulting in a functional fail-
ure. The synchronous system approach, in which all memory elements in the system are
simultaneously updated using a globally distributed periodic synchronization signal (that
is, a global clock signal), represents an effective and popular way to enforce this ordering.
Functionality is ensured by imposing some strict contraints on the generation of the clock
signals and their distribution to the memory elements distributed over the chip; -
pliance often leads to malfunction.
This Chapter starts with an overview of the different timing methodologies. The
majority of the text is devoted to the popular synchronous approach. We analyze the
impact of spatial variations of the clock signal, called clock skew, and temporal variations
of the clock signal, called clock j