文档介绍：1 Chapter 10 Problem Set
Chapter 10
PROBLEMS
1. [C, None, ] For the circuit in Figure , assume a unit delay through the Register and
Logic blocks (., tR = tL = 1). Assume that the registers, which are positive edge-triggered,
have a set-up time tS of 1. The delay through the multiplexer tM equals 2 tR.
a. Determine the minimum clock period. Disregard clock skew.
b. Repeat part a, factoring in a nonzero clock skew: δ= t′θ– tθ= 1.
c. Repeat part a, factoring in a non-zero clock skew: δ= t′θ– tθ= 4.
d. Derive the maximum positive clock skew that can be tolerated before the circuit fails.
e. Derive the maximum negative clock skew that can be tolerated before the circuit fails.
Logic Logic Logic
Mux
Register
Register
tθ t′θ
Logic Logic Logic Logic Logic
Θ
Figure Sequential circuit.
2. This problem examines sources of skew and jitter.
a. A balanced clock distribution scheme is shown in Figure . For each source of variation,
identify if it contributes to skew or jitter. Circle your answer in Table
4 Power Supply Noise
3 Interconnect
5 Data Dependent Load
Devices 2
6 Static Temperature Gradient
1 Clock Generation
Figure Sources of Skew and Jitter in Clock Distribution.
2 Chapter 10 Problem Set
1) Uncertainty in the clock generation circuit Skew Jitter
2) Process variation in devices Skew Jitter
3) Interconnect variation Skew Jitter
4) Power Supply Noise Skew Jitter
5) Data Dependent Load Capacitance Skew Jitter
6) Static Temperature Gradient Skew Jitter
Table Sources os Skew and Jitter
b. Consider a Gated Clock implementation where the clock to various logical modules can be
individually turned off as shown in Figure . (., Enable1,..., EnableN can take on dif-
V
DD VDD
Enable
Input Clk Enable Clk
Clock Enable1
Driver
Gated Gated
Clock
Enable Enable Clock
Clk 2 Clk
Clk Enable
EnableN
Fine-grain Clock Gating
Gating Approach A Gating Appro