文档介绍：ASICs...THE COURSE (1 WEEK)
FLOORPLANNING 16
AND
PLACEMENT
Key terms and concepts: The input to floorplanning is the output of system partitioning and
design entry—list. The output of the placement step is a set of directions for the routing
tools.
The starting point for floorplanning and placement for the Viterbi decoder (standard cells).
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2 SECTION 16 FLOORPLANNING AND PLACEMENT ASICS... THE COURSE
The Viterbi decoder after floorplanning and placement.
ASICs... THE COURSE Floorplanning 3
Floorplanning
Key terms and concepts: Interconnect and gate delay both decrease with feature size—but at
different rates • Interconnect capacitance bottoms out at 2pFcm–1 for a minimum-width wire, but
gate delay continues to decrease • Floorplanning predicts interconnect delay by estimating inter-
connect length
Interconnect and gate delays.
As feature sizes decrease, both delay /ns
average interconnect delay and
average gate delay decrease—
but at different rates.
interconnect
This is because interconnect ca- delay
pacitance tends to a limit that is
gate delay
independent of scaling.
Interconnect delay now domi- minimum feature
size/ mm
nates gate delay.
Floorplanning Goals and Objectives
Key terms and concepts: Floorplanning is a mapping between the logical description (the
netlist) and the physical description (the floorplan).
Goals of floorplanning:
• arrange the blocks on a chip,
• decide the location of the I/O pads,
• decide the location and number of the power pads,
• decide the type of power distribution, and
• decide the location and type of clock distribution.
Objectives of floorplanning are:
• to minimize the chip area, and
• minimize delay.
Measurement of Delay in Floorplanning
Key terms and concepts: To predict performance before plete routing we need to answer
“How long does it takes to get from Russia to China?”• In floorplanning we may even move
Russia and