文档介绍：ASICs...THE COURSE (1 WEEK)
PROGRAMMABLE 5
ASIC LOGIC
CELLS
Key concepts: basic logic cell • multiplexer-based cell • look-up table (LUT) • programmable
array logic (PAL) • influence of programming technology • timing • worst-case design
Actel ACT
ACT 1 Logic Module
Logic Module Logic Module Logic Module
M1 A0 F
A0 D
Actel ACT 0 F1 A1 0
M3 F1
A1 1 '1' 1
SA F1
S 0 0 F
SA F F2 C
M2 1 B0 1
B0 0 S D 0
B1 F2
B1 1 F2 '1' 1
SB
(a) S
SB S3 S0 A
S3
S0 '0'
S1 O1
S1 O1 B
F=(A ·B) +(B' ·C)+D
(b) (c) (d)
The Actel ACT architecture
(a) Organization of the basic logic cells
(b) The ACT 1 Logic Module (LM, the Actel basic logic cell). The ACT 1 family uses just
one type of LM. ACT 2 and ACT 3 FPGA families both use two different types of LM
(c) An example LM implementation using pass transistors (without any buffering)
(d) An example logic macro. Connect logic signals to some or all of the LM inputs, the re-
maining inputs to VDD or GND
1
2 SECTION 5 PROGRAMMABLE ASIC LOGIC CELLS ASICS... THE COURSE
Shannon’s Expansion Theorem
• We can use the Shannon expansion theorem to expand F =A·F(A='1') +
A'·F(A='0')
Example: F =A'·B + A·B·C' + A'·B'·C = A·(B·C') + A'·(B + B'·C)
• F(A='1')=B·C' is the cofactor of F with respect to (wrt) A or FA
• If we expand F wrt B, F =A'·B + A·B·C' + A'·B'·C = B·(A' + A·C') + B'·(A'·C)
• Eventually we reach the unique canonical form, which uses only minterms
•(A minterm is a product term that contains all the variables of F—such as A·B'·C)
Another example: F=(A·B) + (B'·C) + D
• Expand F wrt B: F=B·(A + D) + B'·(C + D) =B·F2 + B'·F1
• F = 2:1 MUX, with B selecting between two inputs: F(A='1') and F(A='0')
• F also describes the output of the ACT 1 LM
• Now we need to split up F1 and F2
• Expand F2 wrt A, and F1 wrt C: F2=A + D=(A·1) + (A'·D); F1=C + D=(C·1) + (C'·D)
• A, B, C connect to the select lines and '1' and D are the inputs of the MUX