文档介绍：EDA 技术实用教程
第 12 章
系统仿真
仿真
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仿真也称模拟(Simulation)
是对电路设计的一种间接的检测方法,是利用计算机对整个硬件系统进行模拟检测,但却可以不接触具体的硬件系统。
VHDL源程序仿真
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图12-1 VHDL仿真流程
VHDL源程序仿真
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【例12-1】
LIBRARY IEEE;
USE ;
ENTITY and1 IS
PORT(aaa,bbb : IN STD_LOGIC; ccc: OUT STD_LOGIC);
END and1;
ARCHITECTURE one OF and1 IS
c <= aaa AND bbb;
END;
VHDL源程序仿真
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【例12-2】
LIBRARY IEEE;
USE ;
ENTITY TRIBUF_and1 IS
GENERIC (
ttri: TIME := 1 ns;
ttxz: TIME := 1 ns;
ttzx: TIME := 1 ns);
PORT (
in1 : IN std_logic;
oe : IN std_logic;
y : OUT std_logic);
END TRIBUF_and1;
ARCHITECTURE behavior OF TRIBUF_and1 IS
BEGIN
PROCESS (in1, oe)
BEGIN
IF oe‘EVENT THEN (接下页)
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IF oe = '0' THEN
y <= TRANSPORT 'Z' AFTER ttxz;
ELSIF oe = '1' THEN
y <= TRANSPORT in1 AFTER ttzx;
END IF;
ELSIF oe = '1' THEN
y <= TRANSPORT in1 AFTER ttri;
ELSIF oe = '0' THEN
y <= TRANSPORT 'Z' AFTER ttxz;
END IF;
END PROCESS;
END behavior;
LIBRARY IEEE;
USE ;
USE ;
ENTITY and1 IS
PORT (
aaa : IN std_logic;
bbb : IN std_logic;
ccc : OUT std_logic);
END and1;
ARCHITECTURE EPF10K10LC84_a3 OF and1 IS
. . . . . .
END EPF10K10LC84_a3;
仿真激励信号的产生
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【例12-3】
LIBRARY IEEE;
USE ;
ENTITY ADDER4 IS
PORT ( a, b : IN INTEGER RANGE 0 TO 15;
c : OUT INTEGER RANGE 0 TO 15 );
END ADDER4;
ARCHITECTURE one OF ADDER4 IS
BEGIN
c <= a + b;
END one;
第一种方法:
仿真激励信号的产生
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【例12-4】
ENTITY SIGGEN IS
PORT ( sig1 : OUT INTEGER RANGE 0 TO 15;
sig2 : OUT INTEGER RANGE 0 TO 15 );
END;
ARCHITECTURE Sim OF SIGGEN IS
BEGIN
sig1 <= 10, 5 AFTER 200 ns, 8 AFTER 400 ns;
sig2 <= 3, 4 AFTER 100 ns, 6 AFTER 300 ns;
END;
仿真激励信号的产生
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图12-2 SIGGEN的仿真输出波形
仿真激励信号的产生
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【例12-5】
ENTITY BENCH IS
END;
ARCHITECTURE one OF BENCH IS
COMPONENT ADDER4
PORT ( a, b : integer range 0 to 15;
c : OUT INTEGER RANGE 0 TO 15 );
PONENT;
COMPONENT SIGGEN
PORT ( sig1 : OUT INTEGER RANGE