文档介绍：第9章第2节 Quartus II中的优化设计 配置、仿真和报告 <EDA技术与应用> 课程讲义
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时序分析的基本概念和术语
Quartus II中的时序约束设置
Quartus II中的时序分析
Quartus II中的编译报告
FPGA芯片的时序指标举例
有关时序分析更多的资料请参见rtushelp/?keyword=verificationanalysis
时序分析的基本概念和术语
时钟建立时间(tSU:clock setup time)
时钟保持时间(th:clock hold time)
时钟输出延时(tCO :Clock to output delay)
时钟偏斜( Clock Skew)
引脚到引脚的延时(tPD: Pin-to-Pin Delay)
时序裕量(Slack)
独立时钟和衍生时钟(Absolute Clock & Derived Clock)
占空比(Duty Cycle)
行波时钟(Ripple Clock)
建立时间和保持时间
tSU= Data Delay + Micro tSU - Clock Delay
tSU (clock setup time)
tH=Clock Delay + Micro tH - Data Delay
tH (clock hold time)
tCO (Clock to output delay)
tCO=Clock Delay+Micro Tco+Data Delay
时钟偏斜(clock skew):图示
时钟偏斜(clock skew)
The difference in the arrival time of a clock signal at two different registers,
which can be caused by path length differences between two clock paths,
or by using gated or rippled clocks.
Clock skew is the mon cause of internal hold violations, as shown in figure 1
引脚间延时tPD (pin-to-pin delay)
The time required for a signal from an input pin to propagate binational logic and appear at an external output pin.
In the Quartus® II software, you can specify the required tPD for the entire project and/or for any
input pin,
output pin,
bidirectional pin.
You can also assign a point-to-point tPD assignment to specify the required delay between
an input pin and a register,
a register and a register,
a register and an output pin.