文档介绍：COPPER METALLIZATION OF SEMICONDUCTOR INTERCONNECTS –
-- ISSUES AND PROSPECTS
Uziel Landau
Chemical Engineering Department
and
The Yeager Center for Electrochemical Sciences
Case Western Reserve University, Cleveland, OH 44106
The copper electroplating process for ‘dual damascene’ metallization of
semiconductor interconnects is critically reviewed and the breakthroughs
that made this process possible are examined. Special emphasis is placed
on analyzing the critical issues, barriers, and future prospects for this
technology. The parameters that control the deposit thickness distribution
on the macroscopic (wafer) scale and on the microscopic (via) scale are
compared. Effects due to the resistive seed layer and mass transport
limitations, particularly on the micro-scale, are analyzed. Preferred
positions, including the effects of plating additives are
discussed. Issues pertaining to cell design, scaling and preferred process
conditions are considered.
Electroplating applications in microelectronics have been traditionally limited, with a
few exceptions, to the metallization of printed wiring boards, contacts, and chip carriers,
and to the fabrication of ic storage devices. Chip level metallization and
particularly the extensive work that carries signals between the
individual transistors have been fabricated exclusively of aluminum or aluminum-
copper alloys using vapor-phase (‘dry’) techniques. This situation has been undergoing
a remarkable change in the past two years following IBM’s striking announcement [1,2]
of mitment to replace the conventional vapor deposited aluminum by
electroplated copper. This paradigm shift has now been incorporated into Sematech’s
road map [3] and is being integrated, worldwide, into production. mercial
implementation of the plating process in an industry that has been skeptical of wet
processing is quite remarkable.
RATIONALE AND ADVANTAGES OF COPPER