文档介绍：Outline
Why low power
Sources of power consumption
Low power design methodology
Low power techniques
Power analysis and tools
Trends in the future
Why Low Power
Potable system - Battery lifetime
Example: mobile phone, PDA, Digital camera
Desktops: high power consumption
Reliability and performance
Need expensive chip package, cooling system
Several deleterious effects
Decreased reliability and performance
Increased cost: packaging cost and cooling system
Exceed power limits of the chip & system
Power, Cost and Heat
Component: silicon and package
Increased die size (wider power busses)
Need better thermal capabilities (package material)
Need better electrical capabilities
System: Cooling and mechanicals
Larger fans
Oversized power supplies
Power limits to the wall
~1100W dc limit
for 110V/20A plug
Challenge of Design as Process Scaling
Source of Power Consumption
Dynamic power consumption
Static power consumption
Key areas of power consumption in SOC
Source of Power Dissipation in CMOS Devices
C = node capacitances
Nsw = switching activities
(number of gate transitions
per clock cycle)
F = frequency of operation
VDD = supply voltage
Qsc = charge carried by
short circuit current
per transition
Ileak = leakage current
Static Power Consumption:
Leakage currents:
Sub-threshold current (I2)
Gate leakage
Gate tunnelling (I4)
Gate induced drain leakage (I3)
pn-junction reverse current (I1)
DC currents
Analog circuit: sense-amps, pull-ups
State dependent
Leakage vs. Process
What will be the dominated leakage current?
Long Channel(L>1um)
Very small leakage
Short channel
(L>180nm,tox>30A)
Subthreshold leakage
Very short channel
(L>90nm, tox>20A)
subthreshold+gate leakage
Nano-scaled(L<90nm,
Tox<20A) Subthreshold
+gate+junction leakage
Sub-threshold leakage current
Has e quite important with technology scaling
Gate leakage current
Is ing important with shrinking device dimensions
PN junction leakage current
Negligible
Outline
Why low power
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