文档介绍：The Case for the
Reduced Instruction puter
David A. Patterson
Computer Science Division
University of California
Berkeley, California 94720
David R. Ditzel
Bell Laboratories
Computing Science Research Center
Murray Hill, New Jersey 07974
INTRODUCTION
One of the primary goals puter architects is to puters that are more cost-
effective than their predecessors. Cost-effectiveness includes the cost of hardware to manufacture
the machine, the cost of programming, and costs incurred related to the architecture in debugging
both the initial hardware and subsequent programs. If we review the history puter families
we find that the mon architectural change is the trend toward ever plex
machines. Presumably this plexity has a positive tradeoff with regard to the cost-
effectiveness of newer models. In this paper we propose that this trend is not always cost-effective,
and in fact, may even do more harm than good. We shall examine the case for a Reduced Instruc-
tion puter (RISC) being as cost-effective as plex Instruction puter (CISC).
This paper will argue that the next generation of puters may be more effectively imple-
mented as RISC's than CISC's.
As examples of this increase plexity, consider the transitions from IBM System/3 to the
System/38 [Utley78] and from the DEC PDP-11 to the VAXll. plexity is indicated quanti-
tative