文档介绍：山东理工大学
毕业设计(论文)
题目:基于CPLD的频率计设计
学院: 电气与电子工程学院
专业: 电子信息工程
学生姓名:
指导教师:
毕业设计(论文)时间:二О一О年 3月 1 日~ 6 月17 日共 16 周
摘要
本文主要论述了利用CPLD进行测频计数,单片机实施控制实现多功能频率计的设计过程。该频率计利用等精度的设计方法,克服了基于传统测频原理的频率计的测量精度随被测信号频率的下降而降低的缺点。等精度的测量方法不但具有较高的测量精度,而且在整个频率区域保持恒定的测试精度。该频率计利用CPLD来实现频率、周期、脉宽和占空比的测量计数。利用单片机完成整个测量电路的测试控制、数据处理和显示输出。并详细论述了硬件电路的组成和单片机的软件控制流程。其中硬件电路包括键控制模块、显示模块、输入信号整形模块以及单片机和CPLD主控模块。
本文详细论述了系统自上而下的设计方法及各部分硬件电路组成及单片机、CPLD的软件编程设计。使用以GW48-CK EDA实验开发系统为主的实验环境下进行了仿真和验证,达到了较高的测量精度。
关键词: 频率计,EDA技术,CPLD,单片机
Abstract
This article discusses the use of frequency counts for CPLD, microcontroller control to achieve the implementation of the design process of multi-frequency meter. The use of such precision frequency meter design ways to e the traditional frequency measurement based on the principle of the measurement precision frequency meter with a decline in the measured signal frequency decreases the ings. And other precision measurement method not only has high accuracy, but in the entire frequency region to maintain a constant precision. The frequency meter using CPLD to implement the frequency, period, pulse width and duty cycle measurement count .I used plete the measurement circuit control, data processing and display output. Then I discussed about position of hardware and microcontroller software control flow. The hardware circuit includes key control module, display module, the input signal shaping module and MCU and CPLD control module.
This paper has particularly described the top-to-bottom design method of the system, the posite of the hardware and the software program device of CPLD and single puter. Under the test environment of the system developed by GW48-CK EDA experiment, the precision and velocity of the measurement have been obtained after the simulation and the test of the hardware.
KEYWORDS: Frequency meter, EDA technique, CPLD, Single puter
目录
摘要 I
Abstract II
目录 III
第一章引言 1
第二章测量原理及其性能指标 2
2
系统设计指标 3
第三章硬件电路设计 4
系统顶层电路设计 4
3.