文档介绍：本科生毕业论文(设计)
题目: 基于VHDL的频率计设计
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单位: 物理科学与信息工程学院
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目录
引言 1
1 EDA 技术发展概况 1
VHDL 软件设计简介 1
VHDL的开发流程 3
MAX+PLUSⅡ开发工具概述 4
2设计实现 5
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7
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10
测频时序控制电路模块 13
15
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22
25
3总结 27
4致谢 28
5参考文献 29
6附录 30
摘要
随着计算机技术超大规模集成电路EDA(Electronics Design Automation)技术的发展和可编程逻辑器件的广泛应用,传统的自下而上的数字电路设计方法、工具器件已远远落后于当今信息技术的发展。基于EDA技术和硬件描述语言的自上而下的设计技术正在承担起越来越多的数字系统设计任务。在电子技术中,频率是最基本的参数之一,并且与许多电参量的测量方案、测量结果都有十分密切的关系,因此频率的测量就显得更为重要。测量频率的方法有多种,其中电子计数器测量频率具有精度高、使用方便、测量迅速,以及便于实现测量过程自动化等优点,是频率测量的重要手段之一。电子计数器测频有两种方式:一是直接测频法,即在一定闸门时间内测量被测信号的脉冲个数;二是间接测频法,如周期测频法。直接测频法适用于高频信号的频率测量,间接测频法适用于低频信号的频率测量。本论文采用自上向下的设计方法,基于VHDL硬件描述语言设计了一种数字频率计,并在Max+plusⅡ平台上进行了仿真。
关键词:EDA;VHDL;数字频率计;CPLD
Abstract
With the development puter,VHDL and EDA and the application of programmable logic devices,the traditional bottom-up design method, tools and devices have been far behind the development of information technology. The top-down design method based on the EDA technology and VHDL is used to design the digital system. Be one of the most fundamental parameter in electron technology medium frequency, parameter measurement scheme, measurement result all have very close something to do with a lot of electricity and, the frequency measurement looks like being more important therefore right away. The method measuring frequency has various, among them the electronic counter measures frequency having accuracy height, usage is convenient, measurement is prompt, easy to realize measurement process automation waits for merit and, counter measures frequency having two kinds way: sure frequency law first directly ,be to measure the pulse number the signal is measured within certain sluice gate time; Two is indirect measure frequency law, if the period measures frequency law, Measure frequency law directly applying to the high frequency signal