文档介绍：UART接口设计及FPGA验证
The Design of UART Interface and FPGA Verification
专业:微电子一班
学生: 指导教师:

摘要:随着电子技术的发展,以及数据传送的需要,通用异步接收/发送器(UART)已成为MCU、CPU、DSP等的基本配置,应用广泛。UART数据通过串行输入、输出,不同装置间通信不需要传送时钟信号,避免了同步传送的时序处理问题,数据线引脚较少,避免了信号间的相互干扰,是未来数据传送的发展方向。本文主要讨论如何应用Verilog HDL语言,基于FPGA器件实现可复用的UART IP Core。通过修改配置文件,用户可以根据需要设置相应的参数,以实现相应功能的UART器件。本设计模块主要包括UART发送器、接收器、波特率发生器,以及总线接口控制逻辑。设计通过Xilinx公司的Spartan-3系列器件XC3S400 FPGA进行功能验证。
关键词:UART、IP核、发送器、接收器、波特率发生器、Verilog HDL
Abstract: With the development of electronic technology, as the need of data transmitter, the Universal Asynchronous Receiver/Transmitter (UART) now is the ponent of MCU, CPU, DSP , etc. By series data input/output, there is no need to send clock signal munication between different equipments, avoiding timing synchronous problem, and the data pin is only one, avoid the disturb among the signals in munication. So, series data transmitting is the development direction in future. This paper focuses on how to use Verilog HDL to carry out reusable UART IP Core, based on FPGA. By modifying the configuration documents, the user can design different ponent. The design is made up of these modules, such as Transmitter, Receiver, Bade_rate generator, and the Bus interface mastering logic. When validating the design, we use XC3S400 FPGA of Xilinx CO.,LTD’s Spartan-3 spectrum.
Key Words: UART , IP Core,Transmitter, Receiver, Verilog HDL
目录
引言……………………………………………………………………1
UART的协议……...................................................................................2
异步通信…………………………………………………………2
…………………………………….3
………………………………………….3
…………………………………………………3
UART的典型应用……………………………………………….5
UART的时钟控制……………………………………………….6
UART的数据采样……………………………………………….6
第三章 UART的硬件设计…………………………………………………….7
UART总体构架………………………………………………….7
UART结构…………………………………………………...7
UART的帧格式………………………………………….…...7
UART 的设计规格……………………………………………8
串行数据发送模块…………………………………………… 11
发送顶层模块…