文档介绍：重庆大学本科学生毕业设计(论文)
4位CMOS流水线ADC的设计
学生:
学号:
指导教师:
专业:
重庆大学光电工程学院
二OO九年六月
Graduation Design(Thesis) of Chongqing University
Design of A 4-Bit CMOS Pipelined ADC
Undergraduate:
Supervisor: Associate Professor Pan Yinsong
Major: Electronic Science And Technology
College Of Optoelectronic Engineering
Chongqing University
June 2009
摘要
随着数字信号处理技术的迅速发展和成熟,将需处理的模拟信号转换成数字信号来进行信号处理的方法得到了越来越广泛的应用。ADC作为连接模拟和数字世界的接口电路,在这种处理方法中占据着十分重要的地位,甚至影响到了数字信号处理技术的应用和推广。此外,作为IC设计主流的CMOS技术的不断发展带来了越来越明显的速度、功耗、和成本优势,特别是SOC技术、数模混合IC设计技术的出现,更是把ADC的设计重新推到了设计的重要地位。
本文设计了一个4位CMOS流水线ADC,采样速率为20MSPS。在了解了CMOS流水线ADC的原理和分析了若干设计的优缺点后,主要做了以下的工作:(1)采用翻转结构的采样保持电路,降低了功耗;(2)采用了数字纠错技术和增益误差校正技术,减小了系统的误差;(3)采用一种动态比较器来提高速度、降低功耗,该动态比较器直流功耗为0;(4)对各个核心单元电路进行了仿真,并结合设计要求进行了优化。研究结果表明,本次设计达到了要求,具有一定的理论价值和应用前景。
关键词:ADC,流水线,采样保持,子ADC,子DAC
ABSTRACT
Because of the rapid development and maturing of digital signal processing technology, to convert the analog signals to digital signals es more and more popular. As a connection of analog and digital circuits, ADC plays a great role in this processing, and even more affects the application and promotion of digital signal processing technology. In addition, the unceasing development of CMOS technology which is a mainstream of IC design brings more and more obvious speed, power, and cost advantages, and especially the SOC technology and mixed-signal IC design techniques turn up, which put the ADC design to the most important status in design.
This paper designs a four bits CMOS pipeline ADC and it’s sampling rate is 20MSPS. By studying the CMOS pipeline ADC’s principle and analyzing the advantages and disadvantages of several designs these things has been done: (1) Using the flip structure sampling circuit to reduce the power consumption; (2) Using the digital correction technology and gain error correction technique, to reduce the error of the system; (3) Using a parators for high speed and lower power consumption, and the parator’s dc power is 0; (4) simulate