文档介绍：原理图输入与 VHDL文本输入设计的区别
Graphic is what you draw is what you get
“ tell me what hardware you want and I will give it to you”
VHDL is what you write is what functional you get
“ tell me how your circuit should behave and the piler will give you the hardware that does the job”
but the designer can not control how the circuit implement
什么是VHDL?
Very high speed integrated Hardware Description Language (VHDL)
是IEEE、工业标准硬件描述语言
用语言的方式而非图形等方式描述硬件电路
容易修改
容易保存
特别适合于设计的电路有:
复杂组合逻辑电路,如:
译码器、编码器、加减法器、多路选择器、地址译码器…...
状态机
等等……..
VHDL的功能和标准
VHDL 描述
输入端口
输出端口
电路的行为和功能
VHDL有过两个标准:
IEEE Std 1076-1987 (called VHDL 1987)
IEEE Std 1076-1993 (called VHDL 1993)
支持行为描述与结构描述的混合使用
描述对象:实体 ENTITY 顶级实体系统模块
低级实体低层次的设计模块
高级实体可将低级实体作为元件调用
实体描述:
实体说明 ENTITY引导,EDN ENTITY 实体名结束
结构体 ARCHITECHTURE引导,END ARCHITECHTURE 结构体名结束
顺序语句:同普通软件,按排列顺序执行
并行语句:无论多少行,同时执行
结构式:
行为式:
算法式:电路和逻辑功能都不知(适用于高层模块,电路实现时可以有多
种不同的实现方案)
例 1 结构式 BEGING u1:nand2 PORT MAP (a=>set,b=>qb,c=>q); u2:nand2 PORT MAP (a=>reset, b=>q, c=>qb);
例 2 行为式
ARCHTECTURE rs_behav OF rsff IS
BEGIN
q<=NOT (qb AND set);
qb<=NOT(q AND reset);
END rs_behav;
例 3 算法式
ARCHTECTURE rs_alg OF rsff IS
BEGIN
ASSERT NOT (reset=“0” AND set=“0”); --输入为00,输出不定,报告错误
REPORT “Input IS ’00’”
SEVERITY error;
IF set=‘1’ AND reset=‘1’THEN 输入为11,输出不变
……….
………
VHDL程序基本结构
VHDL Synthesis vs. other HDLs Synthesis
VHDL: “tell me how your circuit should behave and I will give you hardware that does the job”
ABEL, PALASM, AHDL:
“tell me what hardware you want and I will give it to you”
Why using VHDL instead of Graphic
Easy to Modify
It is more powerful than Graphic
VHDL is a portable language because
is device independent
the same code can be applied to Device manufactured pany A pany B
【例5-1】
ENTITY mux21a IS
PORT( a, b : IN BIT ;
s : IN BIT;
y : OUT BIT ) ;
END ENTITY mux21a ;
ARCHITECTURE one OF mux21a IS
BEGIN
y <= a WHEN s = '0' ELSE
b ;
END ARCHITECTURE one ;
实体
结构体
多路选择器