文档介绍：FPGA跨时钟域设计 -- Multi-Asynchronous Clock Design of FPGA
主要内容
局部同步设计概念
跨时钟域的问题
亚稳态(metastability)
同步失败(synchronize failure)
同步化
同步器(synchronizer)
保持寄存器和握手(hold and handshake)
异步FIFO设计(asynchronous FIFO)
为什么讨论多时钟域设计
全同步设计(totally synchronous)
一个时钟
全异步设计(totally asynchronous)
没有时钟
全局异步,局部同步设计(globally asynchronous,locally synchronous)
多个独立时钟域,同一时钟域内同步
这是我们关心的多时钟域设计
不可避免,单一时钟不能满足设计的需求
亚稳态
什么是亚稳态
引起亚稳态的原因
亚稳态对系统可靠性的危害
如何评估其危害-MTBF
如何减少亚稳态的风险
什么是亚稳态
a metastable output is undefined or oscillates between HIGH and LOW for an indefinite time due to marginal triggering of the circuit. This marginal triggering is usually caused by violating the storage elements’ minimum set-up and hold times.
"When sampling a changing data signal with a clock ... the order of the events determines the smaller the time difference between the events, the longer it takes to determine which came two events occur very close together, the decision process can take longer than the time allotted,and a synchronization failure occurs. "
亚稳态最终收敛于0或1或者振荡
引起亚稳态的原因
在数据跳变期间采样
建立或保持时间不满足
跨时钟域的信号和同步时钟之间的关系不能确定
单一时钟域内工具确保建立保持时间,不出现亚稳态
从tsu ,th和tco的角度看亚稳态