文档介绍：TMS320F206
DIGITAL SIGNAL PROCESSOR
SPRS050A – NOVEMBER 1996 – REVISED APRIL 1998
D High-Performance Static CMOS Technology D 32-Bit ALU/Accumulator
D Includes the T320C2xLP Core CPU D 16 × 16-Bit Multiplier With a 32-Bit Product
D TMS320F206 is a Member of the D Block Moves from Data and Program
TMS320C20x Generation, Which Also Space
Includes the TMS320C203, and D TMS320F206 Peripherals:
TMS320C209 Devices – On-Chip 16-Bit Timer
D Instruction-Cycle Time 50 ns @ 5 V – On-Chip Software-Programmable
D Source patible With TMS320C25 Wait-State (0 to 7) Generator
– On-Chip Oscillator
D Upwardly patible With
– On-Chip Phase-Locked Loop (PLL)
TMS320C5x Devices
D – Six General-Purpose I/O Pins
Three External Interrupts – Full-Duplex Asynchronous Serial Port
D TMS320F206 Integrated Memory: (UART)
– 544 × 16 Words of On-Chip Dual-Access – Enhanced Synchronous Serial Port
Data RAM (ESSP) With Four-Level-Deep FIFOs
×
– 32K 16 Words of On-Chip Flash D Input Clock Options
Memory (EEPROM) – Options – Multiply-by-One, -Two, or -Four
×
– 4K 16 Words of On-Chip Single-Access and Divide-by-Two
Program/Data RAM
D Support of Hardware Wait States
D 224K × 16-Bit Maximum Addressable
D Power Down IDLE Mode
External Memory Space
D †
– 64K Program IEEE -Compatible Scan-Based
– 64K Data Emulation
– 64K Input/Output (I/O) D 100-Pin Thin Quad Flat Package (TQFP)
– 32K Global (PZ Suffix)
description
The TMS320F206 Texas Instruments (TI) digital signal processor (DSP) is fabricated with static CMOS
integrated-circuit technology, and the architectural design is based upon that of the TMS320C20x series,
optimized for low-power operation. bination of advanced Harvard architecture, on-chip peripherals,
on-chip memory, and a highly specialized instruction set is the basis of the operational flexibility and speed of
the ’F206.
The ’F206 offers these advantages:
D 32K 16 words on-chip flash EEPROM reduces