基于CPLD可变模计数器的设计与实现.doc

文档介绍：题目基于CPLD可变模计数器的设计与实现
作者姓名
指导教师
二级学院电气信息工程学院
专业电子信息工程
学号
2012年5月10日
基于CPLD的可变模计数器的设计与实现
摘要
随着电子技术、计算机技术和EDA技术的不断发展,利用FPGA/CPLD进行数字系统的开发已被广泛应用于通信、航天、医疗电子、工业控制等领域。与传统电路设计方法相比,FPGA/CPLD具有功能强大,开发周期短,投资少,便于追踪市场变化及时修改产品设计,以及开发工具智能化等特点。近年来,FPGA/CPLD发展迅速,随着集成电路制造工艺的不断进步,高性价比的FPGA/CPLD器件推陈出新,使FPGA/CPLD成为当今硬件设计的重要途径。在FPGA/CPLD的应用设计开发中,Verilog作为一种主流的硬件描述语言,具有很强的电路描述和建模能力,能从多个层次对数字系统进行建模和描述,从而大大简化了硬件设计任务,提高了设计效率和可靠性,并在语言易读性和层次化、结构化设计方面表现出了强大的生命力和应用潜力。
本论文研究、设计的计数器电路是数字系统中使用最多的时序电路之一,不仅能用于对时钟脉冲计数,还可以用于分频、定时、产生节拍脉冲和脉冲序列以及进行数字运算等。可变模计数器由于计数容量可以根据需要进行变化,为其广泛使用创造了便利。本论文基于复杂可编程逻辑器件CPLD,在Altera QuartusⅡ开发环境下,用Verilog HDL语言设计了一种具有清零、置数、使能控制、可逆计数和具有可变模功能的计数器。
关键词:CPLD;Verilog HDL;可变模计数器
CPLD based design and Realization of the variable modulo counter
Abstract
With the continuous development of electronic technology, computer technology and EDA technology, Digital systems with FPGA/CPLD has been widely used munications, aerospace, medical electronics, industrial control and other fields. Compared with the traditional circuit design, FPGA / CPLD has advantages of powerful, short development cycle, less investment, easy to track changes in the market in a timely manner to modify products design, and intelligent development tools. In recent years, FPGA/CPLD has developed rapidly, with the continuous advancement of integrated circuit manufacturing processes, efficient and cost-effective FPGA/CPLD devices have e a significant way in hardware design. In the application of FPGA/CPLD design, Verilog is acting as a mainstream hardware description language, with the circuit description and modeling capabilities from multiple levels of digital systems modeling and description, which greatly simplifies the hardware design tasks, improves design efficiency and reliability, and makes it easy in structured design. Verilog is demonstrating the great vitality and potential applications.
Counter is one of the most important sequential circuits in digital systems. It not only can be used to m