文档介绍：。(VerilogHDL程序)本程序主要用于测量出输入信号的频率。采用等精度测量的方法,在整个测量范围内误差相同。可以自动切换量程,指示数据小数点的位置和频率单位。当输入信号频率过低时还能发出相应的指示信号,通知CPU做出相应控制。通过适度的采样控制减小了测量误差。modulefrequency(clk,ret,Fx_clr,Fxin,Fout,LF,spoint,flag_MK);inputwireclk,ret;inputwireFxin;//待测频率输入端口inputwireFx_clr;//CPU的控制信号,控制频率计清零outputreg[15:0]Fout;//测得的频率值outputregLF;//低频标志,高电平是表示为低频outputreg[1:0]spoint;//指示小数点的位置outputreg[1:0]flag_MK;//频率单位:M标志K标志wireFx_cph;reg[7:0]cp_ch;regFend;//测频结束标志regFsst;//控制本地标频开始计数的标志0:开始计数reg[39:0]Ns;//对本地标频的计数reg[23:0]LFCH;//低频检测计数器,对底频率和直流做出警报和指示reg[15:0]Nx,Nx1;//对待测频率的计数,Nx1检测低频被测信号的暂存器regs0,s1,s2,s3,s4,s5,s6,s7,s8,sx1000;always@(posedgeclkornegedgeret)if(!ret)beginsx1000<=1'b0;s0<=1'b0;s1<=1'b0;s2<=1'b0;s3<=1'b0;s4<=1'b0;s5<=1'b0;s6<=1'b0;s7<=1'b0;s8<=1'b0;endelsebeginsx1000<=(Nx>=1000);s0<=(Ns==40'd100_0);s1<=(Ns==40'd100_00);s2<=(Ns==40'd100_000);s3<=(Ns==40'd100_000_0);s4<=(Ns==40'd100_000_00);s5<=(Ns==40'd100_000_000);s6<=(Ns==40'd100_000_000_0);s7<=(Ns==40'd100_000_000_00);s8<=(Ns>=40'd100_000_000_000);endalways@(posedgeclkornegedgeret)if(!ret)beginFend<=1'b0;flag_MK<=2'b00;spoint<=2'b00;Fout<=16'h0000;endelsebeginif(Fend)Fend<=1'b0;if(Fx_clr)Fend<=1'b1;if(sx1000)case({s0,s1,s2,s3,s4,s5,s6,s7,s8})//--F-sp-MK9'b10_0000_000:{Fout,Fend,spoint,flag_MK}<={Nx,5'b1_01_10};9'b01_0000_000:{Fout,Fend,spoint,flag_MK}<={Nx,5'b1_10_10};9'b00_1000_000:{Fout,Fend,spoint,flag_MK}<={Nx,5'b1_11_10};9'b00_0100_000:{Fout,Fend,spoint,flag_MK}<={Nx,5'b1_01_01};9'b00_0010_000:{Fout,Fend,spoint,flag_MK}<={Nx,5'b1_10_01};9'b00_0001_000:{Fout,Fend,spoint,flag_MK}<={Nx,5'b1_11_01};9'b00_0000_100:{Fout,Fend,spoint,flag_MK}<={Nx,5'b1_01_00};9'b00_0000_010:{Fout,Fend,spoint,flag_MK}<={Nx,5'b1_10_00};9'b00_0000_001:{Fout,Fend,spoint,flag_MK}<={Nx,5'b1_11_00};endcaseendalways@(posedgeclkorposedgeFend)if(Fend)beginLFCH<=24'h000000;LF<=1'b0;endelsebeginLFCH<=LFCH+1'b1;if(LFCH==24'd100_000_00)beginLF<=(Nx1==Nx);LFCH<=24'h000000;endif(LFCH==24'd0)Nx1<=Nx;endalways@(pose