文档介绍：、熟悉Verilog语言的编写。2、掌握计算机的每个部件的构成逻辑及工作原理,计算机各部件之间的连接逻辑,计算机整机的工作原理。3、掌握CPU功能。4、设计55条单周期指令CPU下板成功2、.p( inputclock, inputresetn, output[2:0]r, output[2:0]g, output[1:0]b, outpuths, outputvs,);(input[31:0]a,input[31:0]b,input[3:0]aluc,output[31:0]r,outputzero,//零标志 outputcarry,//进位标志位 outputnegative,//负数标志位 outputoverflow//溢出标志位); wire[31:0]d_and=a&b;//0100 wire[31:0]d_or=a|b;//0101 wire[31:0]d_xor=a^b;//0110 wire[31:0]d_nor=~(a|b);//0111 wire[31:0]d_lui={b[15:0],16'h0};//100x wire[31:0]d_slt=a<b?1:0; wire[31:0]d_sltu=(a[31]&&~b[31])||(a[31]&&b[31]&&a>b)||(~a[31]&&~b[31]&&a<b); wire[31:0]d_and_or=aluc[0]?d_or:d_and; wire[31:0]d_xor_nor=aluc[0]?d_nor:d_xor; wire[31:0]d_and_or_xor_nor=aluc[1]?d_xor_nor:d_and_or; wire[31:0]d_slt_sltu=aluc[0]?d_slt:d_sltu; wire[31:0]d_lui_slt_sltu=aluc[1]?d_slt_sltu:d_lui; wire[31:0]d_as; wire[31:0]d_sh; wirecarry_as; wirenegative_as; wireoverflow_as; wirecarry_sh; addsub32as32(a,b,aluc[0],aluc[1],d_as,carry_as,overflow_as); shiftshifter(b,a[4:0],~aluc[1],~aluc[0],d_sh,carry_sh); mux4x32select_d(d_as,d_and_or_xor_nor,d_lui_slt_sltu,d_sh,aluc[3:2],r); mux4x1select_carry(carry_as,1'b0,1'b0,carry_sh,aluc[3:2],carry); mux4x1select_overflow(overflow_as,1'b0,1'b0,overflow_sh,aluc[3:2],overflow); assignzero=~|r; assignnegative=r[31];endmodule (input[4:0]raddr1,input[4:0]raddr2,input[31:0]wdata,input[4:0]waddr,inputwe,inputclk,inputrst,output[31:0]radata1,output[31:0]radata2); reg[31:0]register[0:31]; assignradata1=(raddr1==0)?0:register[raddr1]; assignradata2=(raddr2==0)?0:register[raddr2]; integeri; always@(posedgerstornegedgeclk)begin if(rst==1) begin for(i=1;i<32;i=i+1)begin register[i]<=0; end end elsebegin register[0]<=32'b0; if((waddr!=0)&&we)begin register[waddr]<=wdata; end end (inputclk,input[4:0]C0adr,input[31:0]C0Wdata,inputC0Write, input[31:0]InteCause, inputInterrupt, ept, output[31:0