文档介绍：右移移位寄存器(高位补1)
module right(CLK,QB,DIN,LOAD);
input CLK,LOAD;
input [7:0] DIN;
output QB;
reg [7:0] REG8;
always @(posedge CLK)begin
if(LOAD) REG8<=DIN;
else REG8[6:0]<=REG8[7:1];end
assign QB=REG8[0] ;
endmodule
左移移位寄存器(低位补零)
module left(CLK,QB,DIN,LOAD);
input CLK,LOAD;
input [7:0] DIN;
output QB;
reg [7:0] REG8;
always @(posedge CLK)begin
if(LOAD) REG8<=DIN;
else REG8[7:1]<=REG8[6:0];end
assign QB=REG8[7] ;
endmodule
循环左移
module sleft(CLK,QB,DIN,LOAD);
input CLK,LOAD;
input [7:0] DIN;
output QB;
reg [7:0] REG8;
always @(posedge CLK)begin
if(LOAD) REG8<=DIN;
else begin REG8[0]<=REG8[7]; REG8[7:1]<=REG8[6:0];end
end
assign QB=REG8;
endmodule
循环右移
module sright(CLK,QB,DIN,LOAD);
input CLK,LOAD;
input [7:0] DIN;
output[7:0] QB;
reg [7:0] REG8;
always @(posedge CLK)begin
if(LOAD) REG8<=DIN;
else begin REG8[7]<=REG8[0]; REG8[6:0]<=REG8[7:1];end
end
assign QB=REG8;
endmodule