文档介绍：西安电子科技大学
硕士学位论文
卷积码及其Viterbi译码的FPGA设计与实现
姓名:王连成
申请学位级别:硕士
专业:电路与系统
指导教师:杨刚
20100101
摘要
摘要
信号在信道中传输不可避免地会受到干扰,为了提高信号传输的可靠性,需
要进行信道纠错编码。其中卷积码由于其出色的纠错性能而得到了广泛使用。
Viterbi译码算法是一种卷积码的最大似然译码算法,通过寻找译码器接收序列和卷
积编码器的输出序列之间的最大似然函数来得出译码结果。
本文用Verilog硬件描述语言设计、开发了一个可在电力线通信(PLC)系统中
使用的编码、译码系统,编、译码分别采用的是(2,1,7)卷积编码及其Viterbi译码。
本文的主要工作:
首先对信道编码技术进行了研究,对卷积码的原理进行了分析,接着着重阐
述了Viterbi译码的算法,并讨论了几种改进算法性能的方法,然后针对(2,1,7)卷积
码的Viterbi译码器进行了结构分析和模块划分,并用Verilog语言在Quartus II平台上
对卷积码编码器和Viterbi译码器的各个模块进行设计。最后给出了用ModelSim仿
真的结果,验证了设计的正确性。

关键词:卷积码 Verilog 硬件描述语言 Viterbi 译码
Abstract
Abstract
Signals are always interfered with noise during transmission in the channel. In
order to improve the reliability of signal transmission, channel error-correcting code is
needed. Convolutional code is widely used because of its outstanding error-correcting
performance. The Viterbi algorithm is a maximum-likelihood decoding algorithm for
convolutional codes. The Viterbi decoder attempts to find the maximum-likelihood
function of the decoded code word against received code word to abtain the results.
This paper designs and implements a Viterbi encoding-decoding system used in
power munication system with Verilog hardware description language, the
Viterbi algorithm used here adopts the (2,1,7) convolutional codes. The paper includes
the following work:
Firstly, the channel coding technique is introduced, and the principle of
convolutional codes is presented. Secondly, the Viterbi decoding algorithm is
emphatically analyzed and several ways to improve the algorithm’s performance are
introduced. Finally, the structure of (2,1,7) Viterbi decoder is discussed. Based on the
above analyses, the convolutional encoder and each module of the Viterbi decoder are
designed with Verilog hardware description language in Quartus II platform. Through
the simulation results in MedolSim,the Viterbi decoder’s correctness can be proved.

Keyword: convolution