文档介绍： 月 ,MAX+PLUS2软件。,因而可根据半加器的电路或真值表写出或门和半加器的VHDL描述。:真值表(CASE语句)描述真值表:absoco00000**********    代码:LIBRARYIEEE;;ENTITYh_adderISPORT(a,b:INSTD_LOGIC;co,so:OUTSTD_LOGIC);ENDENTITYh_adder;ARCHITECTUREfh1OFh_adderISBEGINso<=NOT(aXOR(NOTb));co<=aANDB;ENDARCHITECTUREfh1;或门逻辑描述:代码:LIBRARYIEEE;;ENTITYor2aISPORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDENTITYor2a;ARCHITECTUREoneOFor2aISBEGINc<=aORb;ENDARCHITECTUREone;一位二进制全加器顶层设计描述:真值表:abci-1sumci00000011100001001101100101110**********     代码:LIBRARYIEEE;;ENTITYf_adderISPORT(ain,bin,cin:INSTD_LOGIC;cout,sum:OUTSTD_LOGIC);ENDENTITYf_adder;PONENTh_adderPORT(a