文档介绍：-1-摘要近些年来,随着微电子技术的发展,可编程逻辑器件在集成度、速度等性能方面也获得了空前的发展,数字频率计是数字信号处理中的重要内容之一,本文主要研究了如何使用FPGA设计和实现数字频率计,详细论述了利用VHDL硬件描述语言设计,并在EDA(电子设计自动化)工具的帮助下,用大规模可编程逻辑器件(FPGA/CPLD)实现数字频率计的设计原理及相关程序。特点是:无论底层还是顶层文件均用VHDL语言编写,避免了用电路图形式设计时所引起的毛刺现象;改变了以往数字电路小规模多器件组合的设计方法,整个频率计设计在一块FPGA/CPLD芯片上,与用其他方法做成的频率计相比,体积更小,性能更可靠。关键字:数字频率计;电子设计自动化;大规模可编程逻辑器-2-AbstractWiththedevelopmentofthemicroelectronictechnology,,discussesdigitalcymometerdesignprinciplesandproceduresbyusingVHDLhardwaredescriptiveprogramming,EDAtoolsandonthebasisofgrandscaleprogrammablelogicdeviceFPGA/’sandtop’sdocumentsarewrittenbyVHDLprogramming,whichavoids“roughphenomenon”,,thewholecymometerisdesignedonaFPGA/paredwithothercymometer,:digitalcymometer;EDA;FPGA/CPLD-3-目录摘要..............................................................................................................................................-1-Abstract...........................................................................................................................................-2-目录................................................................................................................................................-3-第1章绪论............................................................................................................................-4-................................................................................................................................-4-................................................................................................-5-...............................................................................................-6-..............