High Performance Computing Risc Architectures, Optimization & Benchmarks, Second Edition.pdf

文档介绍：RISC Architectures, Optimization
& Benchmarks
F318233
O'REILLY Kevin Dowd & Charles Severance
High puting
Second Edition
Kevin Dowd & Charles R. Severance
O'REILLY"
Cambridge • Koln • Paris • Sebastopol • Tokyo
Table of Contents
Preface xi
I: puter Architectures i
1: What Is High puting? 3
Why Worry About Performance? 3
Scope of High puting 4
Studying High puting 5
Measuring Performance 6
The Next Step 6
2: High Performance Microprocessors 8
Why CISC? 9
Fundamentals of RISC 11
Second-Generation RISC Processors 22
RISC Means Fast 25
Out-of-Order Execution: The Post-RISC Architecture 25
Future Trends: Intel IA-64 and EPIC 28
Closing Notes 29
3: Memory 31
Memory Technology 32
Registers 34
Caches 35
anization 39
Table of Contents
Virtual Memory 43
Improving Memory Performance 47
Closing Notes 56
4: Floating-Point Numbers 58
Reality 58
Representation 59
Effects of Floating-Point Representation 63
Improving Accuracy Using Guard Digits 67
History of IEEE Floating-Point Format 68
IEEE Floating-Point Standard 69
IEEE Storage Format 69
IEEE Operations 71
Special Values 73
Exceptions and Traps 75
Compiler Issues 75
Closing Notes 76
II: Programming and Tuning Software 79
5: What piler Does 81
History pilers 82
Which Language to Optimize? 83
piler Tour 65
Optimization Levels 89
Classical Optimizations 91
Closing Notes 98
6: Timing and Profiling 100
Timing 101
Subroutine Profiling 108
Basic Block Profilers 120
Virtual Memory 123
Closing Notes 125
7: Eliminating Clutter 128
Subroutine Calls 129
Branches 134
Branches Within Loops 134
Table of Contents
Other Clutter 139
Closing Notes 144
8: Loop Optimizations 146
Operation Counting 147
Basic Loop Unrolling 149
Qualifying Candidates for Loop Unrolling 150
Nested Loops 153
Loop Interchange 156
Memory Access Patterns 157
When Interchange Won't Work 160
Blocking to Ease Memory Access Patterns 161