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Standardized Functional Verification - A. Wiemann (Springer, 2010).pdf

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文档介绍

文档介绍:Standardized Functional
Verification
Alan Wiemann

Standardized Functional
Verification
Alan Wiemann
San Carlos, CA
USA







ISBN 978-0-387-71732-6 e-ISBN 978-0-387-71733-3

Library of Congress Control Number: 2007929789

© 2008 Springer Science+Business Media, LLC
All rights reserved. This work may not be translated or copied in whole or in part without the written
permission of the publisher (Springer Science+Business Media, LLC, 233 Spring Street, New York, NY
10013, USA), except for brief excerpts in connection with reviews or scholarly analysis. Use in
connection with any form of information storage and retrieval, electronic adaptation, computer software,
or by similar or dissimilar methodology now known or hereafter developed is forbidden. The use in this
publication of trade names, trademarks, service marks and similar terms, even if they are not identified as
such, is not to be taken as an expression of opinion as to whether or not they are subject to proprietary
rights.

Printed on acid-free paper.


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Preface
It’s widely known that, in the development of integrated circuits, the
amount of time and resources spent on verification easily exceeds that
spent on design. A survey of current literature finds numerous references
to this fact.
A whitepaper from one major pany states that, “Design teams
reportedly spend as much as 50 to 70 percent of their time and resources in
the functional verification effort.” A brief paper from Design and Reuse
observes that, “70 percent of the overall design phase is dedicated to
verification,” and that, “as designs double in size, the verification effort
can easily quadruple.” In spite of all this effort, another whitepaper from
yet another pany observes that, “two or three very expensive
silicon iterations are the norm today.”
Couple these observations on verification effort with the fervent quest
for functio