文档介绍：Lecture Notes puter Science 2963
Edited by G. Goos, J. Hartmanis, and J. van Leeuwen
Springer
Berlin
Heidelberg
New York
Hong Kong
London
Milan
Paris
Tokyo
Richard Sharp
Higher-Level
Hardware Synthesis
Springer
eBook ISBN: 3-540-24657-6
Print ISBN: 3-540-21306-6
©2005 Springer Science + Business Media, Inc.
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Preface
In the mid 1960s, when a single chip contained an average of 50 transistors,
Gordon Moore observed that integrated circuits were doubling plexity
every year. In an influential article published by Electronics Magazine in 1965,
Moore predicted that this trend would continue for the next 10 years. Despite
being criticized for its “unrealistic optimism,” Moore’s prediction has remained
valid for far longer than even he imagined: today, chips built using state-of-
the-art techniques typically contain several million transistors. The advances in
fabrication technology that have supported Moore’s law for four decades have
fuelled puter revolution. However, this exponential increase in transistor
density poses new design challenges to engineers puter scientists alike.
New techniques for plexity must be developed if circuits are to
take full advantage of the vast numbers of transistors available.
In this monograph we investigate both (i) the design of high-level languages
for hardware description, and (ii) techniques involved in translating these high-
level languages to silicon. We propose SAFL, a first-order functional language
designed specifically for behavioral hardware description, and des