文档介绍：Therearememorydevicesinthecircuits; theoutputrelyonbothinputsandstates!Chapter7SequentiallogicdesignprinciplesBasicmemorydevicesLatch:theinputsbewatchedcontinuouslyandoutputmaybechangedatanytimeindependentoftheclock; Flip-flop:theinputbesampledandoutputmaybechangedonlyatthetimesdeterminedbytheclock!(Q)canbehold,butcannotbeset!S-RlatchwhenbothSandRis(00),thestatehold! WhenSR=(10)Set:setQ=1 WhenSR=(01)Reset:setQ=atesinsteadinverters:gettwoinputsThetimedelayinS-RlatchWeneedtimetosetupastablestate!Initialstate:Q=0Laststate:Q=1Ifinputfrom11to00Theinput(11)shouldbeavoided!Initialstate:Q=0QN=0Laststate:Q=?QN=?MetastableIfinputsignalistooshortInitialstate:Q=0Laststate:metastableS-RlatchWheninputspulseistooshort:metastable!Minimum-pulse-widthtpw(min): inputholdtimetoavoidmetastable!S-RlatchUseNANDgates:WhenS=R=1,bothoutputsare1,plementary!S-RlatchwithenableUseANDgatestocontroltheinputsWhenC=1,itisanormalS-Rlatch; WhenC=0,bothinputsarecutoff,andthestateishold!