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Instruction tables Lists of instruction latencies.pdf

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文档介绍:Introduction Page 1 4 By Agner Fog. Technical University of Denmark. Copyright ? 1996 - 2013. Last updated 2013-04-03. Introduction This is the fourth in a series of five manuals: 2. Optimizing subroutines in assembly language: An optimization guide for x86 platforms. 5. Calling conventions for different C++ compilers and operating systems. Instruction tables Lists of instruction latencies, throughputs and micro-operation break- downs for Intel, AMD and VIA CPUs 1. Optimizing software in C++: An optimization guide for Windows, Linux and Mac platforms. 3. The microarchitecture of Intel, AMD and VIA CPUs: An optimization guide for assembly programmers piler makers. 4. Instruction tables: Lists of instruction latencies, throughputs and micro-operation breakdowns for Intel, AMD and VIA CPUs. The latest versions of these manuals are always available from imize. Copyright conditions are listed below. The present manual contains tables of instruction latencies, throughputs and micro-operation breakdown and other tables for x86 family microprocessors from Intel, AMD and VIA. The figures in the instruction tables represent the results of my measurements rather than the offi- cial values published by microprocessor vendors. Some values in my tables are higher or lower than the values published elsewhere. The discrepancies can be explained by the following factors: ● My figures are experimental values while figures published by microprocessor vendors may be based on theory or simulations. ● My figures are obtained with a particular test method under particular conditions. It is possible that different values can be obtained under other conditions. ● Some latencies are difficult or impossible to measure accurately, especially for memory access and type conversions that cannot be chained. ● Latencies for moving data from one execution unit to another are listed explicitly in some of my tables while they are included in the general latencies in some tables published

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