文档介绍：Quartus® II Software Design Series: Timing Analysis
- Timing analysis basics
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Objectives
Display a plete understanding of timing analysis
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How does timing verification work?
Every device path in design must be analyzed with respect to timing specifications/requirements
Catch timing-related errors faster and easier than gate-level simulation & board testing
Designer must enter timing requirements & exceptions
Used to guide fitter during placement & routing
Used to pare against actual results
IN
CLK
OUT
D
Q
CLR
PRE
D
Q
CLR
PRE
binational delays
CLR
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Timing Analysis Basics
Launch vs. latch edges
Setup & hold times
Data & clock arrival time
Data required time
Setup & hold slack analysis
I/O analysis
Recovery & removal
Timing models
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Path & Analysis Types
Three types of Paths:
Clock Paths
Data Path
Asynchronous Paths*
Clock Paths
Async Path
Data Path
Async Path
D
Q
CLR
PRE
D
Q
CLR
PRE
Two types of Analysis:
Synchronous – clock & data paths
Asynchronous* – clock & async paths
*Asynchronous refers to signals feeding the asynchronous control ports of the registers
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Launch & Latch Edges
CLK
Launch Edge
Latch Edge
Data Valid
DATA
Launch Edge: the edge which “launches” the data from source register
Latch Edge: the edge which “latches” the data at destination register (with respect to the launch edge, selected by timing analyzer; typically 1 cycle)
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Setup & Hold
Setup: The minimum time data signal must be stable
BEFORE clock edge
Hold: The minimum time data signal must be stable
AFTER clock edge
D
Q
CLR
PRE
CLK
Th
Valid
DATA
Tsu
CLK
DATA
Together, the setup time and hold time form a Data Required Window,
the time around a clock edge in which data must be stable.
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Data Arrival Time
Data Arrival Time = launch edge + Tclk1 + Tco +Tdata
CLK
Tclk1
Data Valid
Tdata
Launch
Edge
Data Valid
Tco
The time fo