文档介绍：中国科学技术大学硕士学位论文分片式处理器一级数据缓存的设计与优化姓名:张军申请学位级别:硕士专业:计算机系统结构指导教师:安虹 20090501 摘要摘要分片式处理器体系结构(TP:A)能够很好地应对纳米工艺代的功耗、线延迟、设计和验证复杂度等一系列问题,是一种具有良好的性能扩展潜力的众核处理器体系结构设计方案。作为一种新型的处理器体系结构,分片式处理器的一级数据高速缓存是决定分片式处理器性能的一个重要因素,面临许多有待深入研究和解决的问题,包括访存延迟、通信和同步、存储二义性,以及可扩展性等。本文探索了分片式处理器()的一级数据高速缓存的设计空间,提出了一种设计方案,并通过对其性能影响因素的量化分析完成了对该设计方案的优化。论文的主要研究内容和成果包括:(1)在充分调研学术界提出的分片式处理器体系结构一级数据缓存设计方案的基础上,。一级数据缓存包含四个体以提高访存带宽,体与体之间的数据按地址交叉存储以减少数据同步,体与体之间的通信通过片上网络来进行。一级数据缓存主要包括Load&Store队列、缺失处理单元、存储依赖预测器等模块。(2),。模拟结果表明改进的存储依赖预测器可以提高大部分应用的存储依赖预测率。(3),。模拟结果表明数据预取机制可以减少访存指令的访存延迟。本文针对SPEC CPU 2000中部分程序的初步实验结果表明:两种优化方案在占用很少的片上资源的情况下可以适应大多数的应用程序。关键词:分片式处理器体系结构一级数据缓存存储依赖预测数据预取 Abstract Abstract Tiled Processor Architecture(TPA),as an novel implementation ofmany-core architecture with good scalability,can cope well with challenges such as power consumption,wire delay,design and plexity in the era of TPA,L DataCache has aconsiderable or even somehow decisive impact onthewhole performance,on which therestillneeds furtherresearch ofissues such as munication and synchronization,memory ambiguity and thisthesis,I explored thedesign space ofL Data cache inTiled Processor Architecture forInstruction levelparallel(TPA—PI),proposed a design framework,and did some optimizations based on aquantitative analysis ofeffect factors toperformance. Contributions ofthisthesisinclude following aspects:(1)After acomprehensive investigation to related works on L Data Cache design of Tiled Processor Architecture SOfar,we proposed anadequate design ofL1Data Cache for our TPA·PI. Inthedesign,the L Data Cache isdivided intofourbanks toincrease thebandwidth ofdata access,and between eachtwo banks interleaving address fordataisadopted to decrease datasynchronizations.(2)Based on the analysis of data dependence characteristics under theblock execution model in