文档介绍：1038 IEEE TRANSACTIONS ON WORKS, VOL. 14, NO. 5, SEPTEMBER 2003
FPGA Implementation of ICA Algorithm for Blind
Signal Separation and Adaptive Noise Canceling
Chang-Min Kim, Hyung-Min Park, Taesu Kim, Yoon-Kyung Choi, and Soo-Young Lee, Member, IEEE
Abstract—An field programmable gate array (FPGA) imple- power in real time. Also, the algorithms are memory intensive
mentation of ponent analysis (ICA) algorithm is and conventional digital signal processor (DSP) architecture
reported for blind signal separation (BSS) and adaptive noise can- is not efficient. Although a few analog VLSI implementations
celing (ANC) in real time. In order to provide puting
power for ICA-based algorithms with multipath reverberation, a had been reported for ICA algorithm, they were applicable to
special digital processor is designed and implemented in FPGA. instantaneous mixtures only and were unable to be utilized for
The chip design fully utilizes modular concept and several chips real-world speech-enhancement applications with convolutive
may be put together plex applications with a large number mixtures [9], [10]. For convolutive BSS problems, only a
of noise sources. Experimental results with a fabricated test board few VLSI architectures had been presented without actual
are reported for ANC only, BSS only, and simultaneous ANC/BSS,
which demonstrates essful speech enhancement i