文档介绍：Guidelines for Designing
High-Speed FPGA PCBs
February 2004, ver. Application Note
Introduction Over the past five years, the development of true analog CMOS processes
has led to the use of high-speed analog devices in the digital arena.
System speeds of 150 MHz and higher have mon for digital
logic. Systems that were considered high end and high speed a few years
ago are now cheaply and easily implemented. However, this integration
of fast system speeds brings with it the challenges of analog system
design to a digital world. This document is a guideline for printed circuit
board (PCB) layouts and designs associated with high-speed systems.
“High speed” does not just mean munication rates (., faster
than 1 gigabit per second (Gbps)). A transistor-transistor logic (TTL)
signal with a 600-ps rise time is also considered a high-speed signal. This
opens up the entire PCB to careful and targeted board simulation and
design. The designer must consider any discontinuities on the board. The
“Time-Domain Reflectometry” and “Discontinuity” sections explain how
to eliminate discontinuities on a PCB. Some sources of discontinuities are
vias, right angled bends, and passive connectors.
The “Termination” section explains about terminations for signals on
PCBs. The placement and selection of termination resistors are critical in
order to avoid reflections.
As systems require higher speeds, they use differential signals instead of
single-ended signals because of better noise margins and immunity.
Differential signals require special attention from PCB designers with
regards to trace layout. The “Trace Layout” section addresses differential
traces in terms of trace layout. Crosstalk, which can adversely affect
single ended and differential signals alike, is also addressed in this
section.
All the dense, high-speed switching (., hundreds of I/O pins switching
at rates faster than 500-ps rise