文档介绍：南京大学毕业论文(设计) 题目: 多功能数字钟南京大学毕业论文(设计) i 摘要近年来,科学技术发展飞速,人们的生活质量也不断提高。传统的时钟已经无法满足现代人的生活要求。多功能数字钟无论在形态还是在性能上都改变了原有的风格。本次设计基于原始的数字钟,在此基础上增加了诸项功能。不仅具备时,分,秒计数功能,另外增加了校时功能,整点报时功能,闹钟功能以及数字跑表功能。设计中采用了 EDA 技术,使用硬件描述语言 Verilog HDL 对各大功能模块的逻辑功能进行代码编写。于 QuartusII 软件环境下,采用层次化设计与模块化设计的方法,由各个功能模块连接建立顶层图,构成基于 FPGA 的多功能数字钟。设计实验板的主芯片为 EP3C25Q240C8 ,多功能数字钟由分频器模块,时钟计数模块,校时控制模块,闹钟模块,整点报时与音乐演奏模块,数据选择模块,译码显示模块,按键去抖动模块和数字跑表模块构成。经过程序编译和模块仿真,在实验板上下载验证,该系统可以完成时,分,秒的正常显示,通过按键切换功能模式,进入闹钟时间设定,校时,数字跑表模式。可以手动调整时间,设定闹钟及数字跑表计时。关键词: FPGA ;Verilog HDL ;数字钟; 南京大学毕业论文(设计) ii THE DIGITAL CLOCK WITH STOPWATCH FUCTION ABSTRACT Inrecent years, the rapid development ofscience technology, quality of life isalso rising. Traditional clock has been unable tomeet the requirements ofmodern life. Both inthe form ofmulti-function digital clock orinthe performance has changed the original style. The design isbased onthe original digital clock, onthe basis ofit increased various functions. Not only have the time, minutes, seconds count function, also add the function ofadjusting time, the whole point timekeeping function, alarm function and digital stopwatch functions. EDA technology used inthe design, using Verilog HDL hardware description language for logic functions inmajor functional modules ofcode towrite. Under Quartus II software environment, using hierarchical design methods and modular design, the top chart established bythe various functional modules connecting each other, constitute FPGA-based multifunctional digital clock. The main system chip ofdesign experiment board isEP3C25Q240C8, multifunctional digital clock posed ofthe divider module, the clock counting module, the adjust t ime control module, the alarm module, the whole point timekeeping and music module, the data selection module, the decoding module, the key tojitter module and digital stopwatch module. After the piled and module simulation, download onthe breadboard validation, The system plete hours, minutes, seconds display properly, through the