文档介绍：四位全加器的VHDL设计
1
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一位全加器真值表
2
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一位全加器的逻辑表达式
S=A⊕B⊕Cin
Co=AB+BCin+ACin
其中A,B为要相加的数，Cin为进位输
入；S为和，Co是进位输出；
3
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Library ieee;
Use ;
Use ;
Entity fulladder Is
Port(Ci,a,b : IN std_logic;
s,Co : OUT std_logic);
End fulladder;
Architecture m1 Of fulladder Is
Signal tmp: std_logic_vector(1 downto 0);
Begin
tmp<=('0' & a) + b + Ci;
s<=tmp(0);
Co<=tmp(1);
End m1;
4
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一位全加器的数据流（逻辑）描述
Library ieee;
Use ;
Use ;
Entity fulladder is
Port (A,B,CI:in std_logic;
S,CO:out std_logic);
End fulladder;
Architecture dataflow of fulladder is
Begin
S<= CI xor A xor B;
CO<= (A and B) or (CI and A) or (CI and B);
End dataflow;
5
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一位全加器的行为描述
Library ieee;
Use ;
Use ;
Entity fulladder is
Port (a,b,cin: In bit;
sum,cout: Out bit);
End fulladder;
Architecture behave Of fulladder Is
Begin
Process (a, b, cin)
Begin
If(a Or b Or cin)= ‘0’ Then
sum <=‘0’;
cout <=‘0’;
Elsif (a AND b AND cin ) =’1’ Then
sum <=‘1’;
cout <=‘1’;
Elsif (a XOR b XOR cin ) =’0’ Then
sum <=‘0’;
cout <=‘1’;
Else
sum <=‘