文档介绍：5 5 4 4 3 3 2 2 1 1 D D C C B B A A CYCLONE FPGA 2. GROUND PLANE1 E. FR4 BOARD MATERIAL AD/DA PORT 3. ALL and CAPACITORS ARE DECOUPLING CAPS UNLESS OTHERWISE NOTED. THEY ARE SHOWN ON THE PAGE WITH THE ICs AND SHOULD BE PLACED NEAR. D. INNER LAYERS OZ CU SWITCH Yao Yuan 08 SRAM C. OUTER LAYERS OZ CU /W OZ AU PLATING AS2830- ,AS2830- EXT PORT ALTERA_AS 10/7/04 07 SDRAM B. 50 +/- 5 OHM MATCHED INPEDANCE 2. CAPACTITANCE VALUES IN FARADS. 06 SYSTEM POWER Initial schematic VGA POWER 1. 采用四层板设计,SDRAM的信号处理要注意等长原则,FPGA的管脚定义可以适当调整,但是SDCLK的位置不能动; 04 CYCLONE IO A. ROUTE TO WITHIN 10% OF MANHATTAN DISTANCE 说明: 05 CYCLONE POWER PROPERTIES: Ready for Layout APPROVED 03 CYCLONE CONFIG USB CHIP NOTES,UNLESS OTHERWISE SPECIFIED: 2. 蓝色边框的单元为接插件,注意与周围器件的间距;右侧为扩展区域,不能有高过8mm的器件; DATE DESCRIPTION 02 CYCLONE CLOCK,PLL & RESET REV 1. TOP - SIGNAL ROUTING FLASH 01 CONNECTORS,UART,LED & OTHERS 布局参考:(具体尺寸根据实际情况而定) 00 NOTES DB9 CLOCK SRAM SCHEMATIC INDEX: H. LAYER STACKUP: 4. BOTTOM - SIGNAL ROUTING G. MINIMUM VIA SIZE 12/20 MILS SDRAM RESET 3. POWER PLANE F. MIMIMUM TRACE WIDTH/SPACING 6 MILS LEDs 1. RESISTANCE VALUES IN OHMS. 09 FLASH EP1C6/EP1C12 PQ240 ALTERA_JTAG EP1C1/4 MAX3232 PS/2 PAGE 04 10/10/04 Yao Yuan Add EA15 Signal Yao Yuan 11/10/04 Add VGA,LCD and ; Change SRAM number Yao Yuan 2/19/05 LCD PORT 16Pin EXT PORT 10 USB IF LCD把 接口增加了背光电源 68013 Clkout FPGA 48MHz 将 芯片的管脚连接到的一个专用输入,用来获得一个的时钟,可以调试 IP PKEND FIFOADDR0; 的核。信号用做 FLAGD 信号用做 FIFOADDR1 Bottom 层,电路修改将 EGPIO11 与 usb——int0 信号相连,一般情况不用。可以作为 i2c 信号 6/15/05 Yao Yuan 2004001 B R e d C y c l o n e I I V 2 . 1 A4 110 Thursday, March 30, 2006 Title Size Document Number Rev Date: Sheet of 5 5 4 4 3 3 2 2 1 1 D D C C B B A A 10 IF <Doc> B Red Cyclone II A 111 Thursday, March 30, 2006 Title Size Document Number Rev Date: Sheet of D+ D- D- D+ SCL SDA UD0 UD1 UD2 UD3 UD4 UD