文档介绍：32 (8) Computer Engineering and Applications 计算机工程与应用
方容•刘加贺•薛志辉•等：卷积神经网络的FPGA并行加速方案设计 (8) #
◎理怡研堯、研发设计◎
卷积神经网络的FPGA并行加速方案设计
方 睿，刘加贺，薛志辉，杨广文
FANG Rui, LIU Jiahe, XUE Zhihui, YANG Guaiigwen
清华大学计算机科学与技术系•北京1000S4
Department of Computer Science and Teclinology, Tsinghua University, Beijing 100084, China
FANG Rui, LIU Jiahe9 XUE Zhihui, et al. FPGA-based design for convolution neural network. Computer Engineering and Applications, 2015, 51(8) :32-36・
Abstract: According to the characteristics of the Convolution Neural Network(CNN), a FPGA-based acceleration pro・ gram which uses deep-pipeline architecture is proposed for the MN：ST data set In this program, theoretically 28 x 28 clock cycles can finish the whole calculation and get the output of the CNN For the propagation stage of the training process, and in the same network structure and tlie same data set, tins FPGA program with 50 MHz &equency can achieve nearly five umes speedup compared to GPU version(Caffe), achieve eight times speedup compared to 12 CPU cores While the FPGA program just costs 26 7% power which GPU version costs
Key words： convolution neural network. Field Programmable Gate Airay( FPGA), deep・pipelme, acceleration
摘 要：， 可以庄一个时钟周期内获得一个计算结果理论上，该方It对于MNIST软据集，在28x28个时钟周期内可以获得一 ，在网络錢构和数据集相同的椅况下，对GPU, FPGA, CPU 进行了