文档介绍：会计学
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第十一低功耗
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Why Low Power
Potable system - Battery lifetime
Example: mobile phone, PDA, Digital camera
Desktops: high power consumption
Reliability and performance
Need expensive chip package, cooling system
Several deleterious effects
Decreased reliability and performance
Increased cost: packaging cost and cooling system
Exceed power limits of the chip & system
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Power, Cost and Heat
Component: silicon and package
Increased die size (wider power busses)
Need better thermal capabilities (package material)
Need better electrical capabilities
System: Cooling and mechanicals
Larger fans
Oversized power supplies
Power limits to the wall
~1100W dc limit
for 110V/20A plug
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Challenge of Design as Process Scaling
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Outline
Why low power
Sources of power consumption
Low power design methodology
Low power techniques
Power analysis and tools
Trends in the future
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Source of Power Consumption
Dynamic power consumption
Static power consumption
Key areas of power consumption in SOC
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Source of Power Dissipation in CMOS Devices
C = node capacitances
Nsw = switching activities
(number of gate transitions
per clock cycle)
F = frequency of operation
VDD = supply voltage
Qsc = charge carried by
short circuit current
per transition
Ileak = leakage current
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Static Power Consumption:
Leakage currents:
Sub-threshold current (I2)
Gate leakage
Gate tunnelling (I4)
Gate induced drain leakage (I3)
pn-junction reverse current (I1)
DC currents
Analog circuit: sense-amps, pull-ups
State dependent
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Leakage vs. Process
What will be the dominated leakage current?
Long Channel(L>1um)
Very small leakage
Short channel
(L>180nm,tox>30A)
Subthreshold leakage
Very short channel
(L>90nm, tox>20A)
subthreshold+gate leakage
Nano-scaled(L<90nm,
Tox<20A) Subthreshold