文档介绍：? 2009 Altera Corporation 1 Quartus ? II Software Design Series: Timing Analysis Quartus ? II Software Design Series: Timing Analysis - Timing analysis basics - Timing analysis basics ? 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 2 Objectives Objectives ? Display plete understanding of timing analysis ? 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 3 How does timing verification work? How does timing verification work? ? Every device path in design must be analyzed with respect to timing specifications/requirements ? Catch timing-related errors faster and easier than gate-level simulation & board testing ? Designer must enter timing requirements & exceptions ? Used to guide fitter during placement & routing ? Used pare against actual results ?? IN CLK OUT DQ CLR PRE DQ CLR binational delays ? CLR ? 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 4 Timing Analysis Basics Timing Analysis Basics ? Launch vs. latch edges ? Setup & hold times ? Data & clock arrival time ? Data required time ? Setup & hold slack analysis ? I/O analysis ? Recovery & removal ? Timing models ? 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademarks of Altera Corporation 5 Path & Analysis Types Path & Analysis Types Three types of Paths: 1. Clock Paths 2. Data Path 3. Asynchronous Paths * Clock Paths Async Path Data Path Async Path DQ CLR PRE DQ CLR PRE Two types of Analysis: 1. Synchronous – clock & data paths 2. Asynchronous *– clock & async paths * Asynchronous refers to signals feeding the asynchronous control ports of the registers ? 2009 Altera Corporation Altera, Stratix, Arria, Cyclone, MAX, HardCopy, Nios, Quartus, and MegaCore are trademark