文档介绍：Microelectronics Reliability 45 (2005) 1021–1032
ate/microrel
Introductory Invited Paper
Optimizing the hot carrier reliability of N-LDMOS
transistor arrays
Douglas Brisbin *, Andy Strachan, Prasad Chaparala
National Semiconductor Corporation, 2900 Semiconductor Drive, Santa Clara, CA 95052-8090, USA
Received 3 November 2004
Available online 30 December 2004
Abstract
Smart power management applications often require operation in the 20–30 V range. These bine
a high performance BiCMOS process with a power lateral DMOS (LDMOS) driver. To obtain high drive current
density and minimal on-resistance (Rdson), LDMOS devices are implemented in transistor arrays. Because of the high
voltages and currents applied to these devices hot carrier degradation is a real reliability concern. This paper dis-
cusses several aspects of N-LDMOS hot carrier reliability including measurement techniques, degradation mecha-
nism, and the effect of both one-dimensional (1-D) and two-dimensional (2-D) layout effects on the hot carrier
degradation behavior of these devices. This paper focuses on device layout optimization rather than process changes
since layout optimization has the advantage of improving performance without impacting other supported devices.
Ó 2004 Elsevier Ltd. All rights reserved.
1. Introduction formed at high stress temperature (150 °C) with either
a high drain voltage or a high gate voltage but no drain
Power management often requires high current IC current flowed through the device during stress. It was
control devices. These devices integrate bipolar, CMOS soon recognized, though, that during switching applica-
and power DMOS on a single chip. The n-channel lat- tions transient bias conditions can cause the DMOS Vgs
eral DMOS (N-LDMOS) is mon choice for the and Vds to be simultaneously high and hot carrier dam-
transistor driver [1–6]. Applications include voltage con- age can occur [7].
verters, mobile phones and appliances. In power