VHDL设计初步第二章语言语法基础.ppt

文档介绍：第二章 VHDL语言语法基础
VHDL入门
例: 2选1选择器设计
a
b mux21 y
s
LIBRARY IEEE;
USE
ENTITY mux21 IS
PORT(a,b:IN STD_LOGIC;
s:IN STD_LOGIC;
y:OUT STD_LOGIC);
END mux21;
ARCHITECTURE one OF mux21 IS
BEGIN
y<=a WHEN s=‘0’ ELSE
b WHEN S=‘1’;
END one;
IEEE库使用说明
器件mux21的外部接口信号说明,PORT相当于器件的引脚,这一部分称为实体
器件mux21的内部工作逻辑描述,即为实体描述的器件功能结构,称为结构体
例: 锁存器设计
LATCH
D Q
ENA
LIBRARY IEEE;
USE ;
ENTITY Latch IS
PORT(D:IN STD_LOGIC;
ENA:IN STD_LOGIC;
Q:OUT STD_LOGIC);
END latch;
ARCHITCTURE one OF latch IS
SIGNAL sig_save:STD_LOGIC;
BEGIN
PROCESS(D,ENA)
BEGIN
IF ENA=‘1’ THEN
sig_save<=D;
END IF;
Q<= sig_save;
END PROCESS;
END one;
锁存器的实体,定义了此器件的输入输出引脚及其信号属性
定义信号
进程语句结构,描述逻辑的时序方式
结构体
例: 全加器设计
1位半加器
1位全加器
H_ADDER
a co
b so
H_ADDER
a co
b so
H_ADDER
a co
b so
F_ADDER
ain cout
bin sum
cin
ain
bin
ain
a
c
b
u1
u2
u3
sum
cout
d
e
f
LIBRARY IEEE;
USE ;
ENTITY or2 IS
PORT(A,B:IN STD_LOGIC;
c: OUT STD_LOGIC);
END or2;
ARCHITECTURE ful OF or2 IS
BEGIN
c <= a OR b;
END fu1;
LIBRARY IEEE;
USE ;
ENTITY h_adder IS
PORT(a,b:IN STD_LOGIC;
co,so:OUT STD_LOGIC);
END h_adder;
ARCHITECTURE fh1 OF h_adder IS
BEGIN
so<= a AND (a NAND b);
co<=NOT( a NAND b );
END fh1;
LIBRARY IEEE;
USE -;
ENTITY f_adder IS
PORT(ain,bin,cin:IN STD_LOGIC;
cout,sum:OUT STD_LOGIC);
END f_adder;
ARCHITECTURE fd1 OF f_adder IS
BEGIN
COMPONENT h_adder
PORT(a,b:IN STD_LOGIC;
co,so:OUT STD_LOGIC);
PONENT;
COMPONENT or2
PORT(a,b:IN STD_LOGIC;
c:OUT STD_LOGIC);
PONENT;
SIGNAL d,e,f:STD_LOGIC;
BEGIN
u1:h_adder PORT MAP(ain,bin,d,e);
u2:h_adder PORT MAP(e,b,f,sum);
u3:or2 PORT MAP(d,f,cout);
END fd1;
元件调用声明
元件连接