文档介绍：Embedded System Design lecture 10 --Processor(2)_hazard _board_verificatioon
Jun WANG
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Contents
Learnt from l and id_ir
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Control Hazard
When CPU decide to branch, other instructions are still in pipeline!!
During the time from branch instruction fetch to branch address generate (from IF to ID to EX to IF, 3 stages),
the 3 instructions followed by branch are in pipeline.
The computing results by them are useless
Should be flushed
or will impact the following instructions computing
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Solution
Software
Insert 3 NOPs
Insert independent operations
Hardware
Flushing
I am not going to more detail…
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Summary
Hazard
Structure
Data
Arithmetic
Software solution
NOP
Hardware solution
Data forwarding
LOAD
Software solution
NOP
Hardware solution
Stall
Control (optional)
Software solution
NOP
Independent operation
Hardware solution
Flushing
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Use hazard to understand test pattern
Control Hazard is an optional topic, you do not need to implement hazard by verilog
but your implementation is highly recommended and scored
Submit by 8th Jan
Data hazard (including forwarding and stall) you MUST finish by 8th Jan, and submit
Both design and test
Understand how to write test pattern for your verilog
Always insert 3 NOPs
But please be more smart…
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Memory implementation
Write verilog by yourself
Use Core_Gernerate to generate IP
Get the verilog built in
If you can use board evaluation in your final project, big plus can give you!
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Concept behind
System on Chip
SOC
From SOB to SOC
System on board to system on chip
SOC
Processor
ARM/DSP/MIPS/X86
Program with C/C++
Memory
FPGA/ASIC
Your own verilog
Therefore, software and hardware division is a problem
New design methodology
SW/HW Co-design
Key of embedded system design
Lets move to next semester
SOPC: (P: programmable)
Newly FPGA, the state-of-art all programmable device, can cover everything with low cost solution, and acceptable performance,
Try
ASIC for further
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