文档介绍：CDNLive! Paper – Signal Integrity (SI for Dual Data Rate (DDR Interface Prithi Ramakrishnan iDEN Subscriber Group Plantaallenging. In addition to incorporating various sections such as Radio Frequency (RF, Power Management, DC, Audio, Digital ICs, and sub-circuits of these modules, design engineers must simultaneously satisfy the rigid placement requirements for components such as speakers, antennas, displays, and cameras. As such, there are very few options and little flexibility in terms of placement of the components. This problem was further accentuated by the fact that several layers of the 10 layer board (3-4-3 structure with one ground plane and no power planes were reserved for power, audio, and other high frequency (RF nets, leaving engineers with few layers to choose from for digital circuitry.
Figure 1. Memory Interface routes With the DDR interface data switching at 266MHz, we had very tight margins — 600ps for data/DQS lines, 280ps for the address lines, and 180ps for control lines. However, with the NAND interface we had larger margins that were on the order of a few tens of nanoseconds. In these situations, choosing a higher drive strength and using terminators of appropriate values (to meet rise times and avoid overshoot/undershoot has become a common practice in DDR designs. However, due to the lack of space on the board, we were not in a position to use terminators. Therefore, we used programmable buffers on our processor, and with the help of Cadence SI tools were able to fine-tune the design. Our group migrated from using Mentor Graphics to Cadence SI during this project. As one might expect, this made the task of designing a high speed DDR interface even more challenging. To help overcome this, we worked extensively with Cadence Services, where Ken Willis supported us on the SI portion of the design. The Source Synchronous Design Challenge Before discussing the specifics of the Motorola DDR interface, a brief overview of source synchronous sig