文档介绍：第 55 卷 第 7 期 天津大学学报(自然科学与工程技术版) Vol. 55 No. 7
2022 年 7 月 comprising two PMOS transistors based on the TSMC 180 nm standard CMOS process using the floating-gate voltage
to characterize the synaptic weight. The floating-gate voltage of one PMOS transistor，which operates in an opto-
electric hybrid mode，increases and decreases under the stimulation of photonic and electrical signals，thus imitating
the excitatory and inhibitory functions of synapses. The other one works in a tunneling mode，and the synaptic weight
is modified through the Fowler-Nordheim(FN)tunneling. Based on the circuit model of the proposed photoelectric
floating-gate synapse，the circuits for pixel recognition and array were designed，and the recognition processes of
binary image“＋”were analyzed without/with noise. Simulation results showed that the designed photoelectric syn-
apse of this paper could realize a binary image in a noise-free situation with basic light intensities of 0 mW/cm2 and
75 mW/cm2 in a noisy situation with the introduction of a mW/cm2 noise. This demonstrates that the proposed pho-
toelectric floating-gate synapse in this paper has a certain antinoise ability.
Keywords：neuromorphic computing；CMOS；photoelectric synapse；floating-gate；synapse weight
为了突破传统冯·